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    METHODS AND APPARATUS TO REDUCE RETIMER LATENCY AND JITTER
    11.
    发明公开
    METHODS AND APPARATUS TO REDUCE RETIMER LATENCY AND JITTER 审中-公开

    公开(公告)号：US20240113851A1

    公开(公告)日：2024-04-04

    申请号：US17956487

    申请日：2022-09-29

    Applicant: Texas Instruments Incorporated

    Inventor： Ani Xavier ,  Jagannathan Venkataraman

    IPC: H04L7/00

    CPC classification number: H04L7/0008

    Abstract: An example system includes: interleaving circuitry including a data input, a plurality of data outputs, and a plurality of clock inputs, the data input coupled to the received data input and each of the plurality of clock inputs coupled to one of the plurality of receiver clock outputs; and handoff circuitry coupled to the interleaving circuitry, the handoff circuitry including: comparison circuitry coupled to the clock generation circuitry and configured to compare the plurality of receiver clocks to the transmission clock; clock configuration circuitry coupled to the comparison circuitry and configured to select one of the plurality of receiver clocks based on the comparison circuitry; and a plurality of flip-flops coupled to the clock configuration circuitry and configured to convert the plurality of data outputs from the plurality of receiver clocks to the transmission clock to generate a plurality of transmission data streams based on the one of the plurality of receiver clocks selected by the clock configuration circuitry.

    Charge pump with output current adjustment
    12.
    发明授权
    Charge pump with output current adjustment 有权

    公开(公告)号：US11722142B1

    公开(公告)日：2023-08-08

    申请号：US17849594

    申请日：2022-06-25

    Applicant: Texas Instruments Incorporated

    Inventor： Jagannathan Venkataraman ,  Ani Xavier ,  Shyam Subramanian

    IPC: H03L7/099

    CPC classification number: H03L7/0992

    Abstract: In described examples, a charge pump includes an output, first and second transistors, a control circuit, a multiplexer, and a calibration circuit. The first transistor's drain is coupled to the output. The second transistor's drain is part of a current path separate from a current path that includes the first transistor's drain. The control circuit generates a control signal in response to voltages at the gates of the first and second transistors. First and second inputs of the multiplexer are respectively coupled to sources of the first and second transistors. A control input of the multiplexer is coupled to receive the control signal. A first input of the calibration circuit is coupled to an output of the multiplexer. A second input of the calibration circuit receives a reference voltage. First and second outputs of the calibration circuit are respectively coupled to body terminals of the first and second transistors.

    Top plate sampling circuit including input-dependent dual clock boost circuits
    18.
    发明授权
    Top plate sampling circuit including input-dependent dual clock boost circuits 有权

    公开(公告)号：US10084466B1

    公开(公告)日：2018-09-25

    申请号：US15856185

    申请日：2017-12-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan

    IPC: H03M1/10 ,  H03M1/12 ,  G06F1/04

    CPC classification number: H03M1/1245 ,  G06F1/04 ,  G11C27/02

    Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

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