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    SYSTEM ON CHIP FIREWALL MEMORY ARCHITECTURE
    12.
    发明申请
    SYSTEM ON CHIP FIREWALL MEMORY ARCHITECTURE 有权

    公开(公告)号：US20240380731A1

    公开(公告)日：2024-11-14

    申请号：US18783999

    申请日：2024-07-25

    Applicant: Texas Instruments Incorporated

    Inventor： Amritpal Singh Mundra ,  Chunhua Hu

    IPC: H04L9/40 ,  G06F21/71 ,  G06F21/76 ,  G06F21/85

    Abstract: Systems and methods provide unified control of firewalls of functional units distributed throughout a system-on-a-chip (SoC) using a configuration controller and security bus. Such unified control enables configuration of a memory to provide a unified view configuration memories of the firewalls, regardless of the locations of the firewalls in the SoC. An example system providing such control includes multiple functional units including multiple firewalls, respectively, in which each firewall stores configuration data for a corresponding functional unit of the functional units; a first bus coupled to the functional units; a second bus that is coupled to the functional units and is electrically isolated from the first bus; and a configuration controller coupled to the second bus and configured to use the second bus to control the configuration data that is stored in each of the firewalls.

    SYSTEM-ON-CHIP (SoC) ASSEMBLY, CONFIGURABLE IP GENERATION AND IP INTEGRATION UTILIZING DISTRIBUTED COMPUTER SYSTEMS
    15.
    发明申请
    SYSTEM-ON-CHIP (SoC) ASSEMBLY, CONFIGURABLE IP GENERATION AND IP INTEGRATION UTILIZING DISTRIBUTED COMPUTER SYSTEMS 有权

    公开(公告)号：US20210160151A1

    公开(公告)日：2021-05-27

    申请号：US17164925

    申请日：2021-02-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Todd Christopher Hiers ,  Chunhua Hu

    IPC: H04L12/24 ,  G06F3/0483 ,  G06F3/0486 ,  G06F30/30

    Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

    System-on-chip (SoC) assembly, configurable IP generation and IP integration utilizing distributed computer systems
    16.
    发明授权
    System-on-chip (SoC) assembly, configurable IP generation and IP integration utilizing distributed computer systems 有权

    公开(公告)号：US10911323B2

    公开(公告)日：2021-02-02

    申请号：US15878978

    申请日：2018-01-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Todd Christopher Hiers ,  Chunhua Hu

    IPC: G06F3/00 ,  H04L12/24 ,  G06F3/0483 ,  G06F3/0486 ,  G06F30/30 ,  G06F3/01

    Abstract: An architecture-specific web-based executable specification tool maintains specification information and metadata for chip and system on a chip (SoC) design. Metadata available in the development ecosystem may be leveraged to improve the specification-to-design process. A unified, integrated environment for subsystem creation, SoC integration, and SoC specification teams is presented using a tool that comprehends SoC constructs. A modern web-based framework (not stand-alone tool) provides collaboration capabilities and allows visual representation and manipulation of data. Connection fabrics (e.g., network on a chip (NoC)) and other project-specific infrastructure can be configured and synthesized on demand and brought in to the design using the common environment. Netlists and other connectivity data can be fed into automated RTL generation processes directly, or used as a reference for implementation design teams. Reports and automated software generation satisfy the needs of the design verification and software teams. Functional and performance testing feedback loops are also provided.

    Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network
    18.
    发明授权
    Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network 有权

    公开(公告)号：US10396922B2

    公开(公告)日：2019-08-27

    申请号：US15891227

    申请日：2018-02-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Eric Hansen ,  Denis Beaudoin ,  Thomas Anton Leyrer

    IPC: H04J3/06 ,  H04L7/00

    Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

    Transmit and receive circuits with multiple interfaces
    19.
    发明授权
    Transmit and receive circuits with multiple interfaces 有权

    公开(公告)号：US12189553B2

    公开(公告)日：2025-01-07

    申请号：US18473391

    申请日：2023-09-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Chunhua Hu ,  Sanand Prasad

    IPC: G06F13/28 ,  G06F13/42

    Abstract: A method includes transmitting first data with a first priority through a first dedicated interface on a transmit side of a PCIe system. The method also includes transmitting second data with a second priority through a second dedicated interface on the transmit side of the PCIe system. The method includes transmitting the first data and the second data to a receive side of the PCIe system using two or more virtual channels over a PCIe link, where the first data uses a first virtual channel and the second data uses a second virtual channel.

    System on chip firewall memory architecture
    20.
    发明授权
    System on chip firewall memory architecture 有权

    公开(公告)号：US12101293B2

    公开(公告)日：2024-09-24

    申请号：US17392497

    申请日：2021-08-03

    Applicant: Texas Instruments Incorporated

    Inventor： Amritpal Singh Mundra ,  Chunhua Hu

    IPC: H04L29/06 ,  G06F21/71 ,  G06F21/76 ,  G06F21/85 ,  H04L9/40

    CPC classification number: H04L63/0218 ,  G06F21/71 ,  G06F21/76 ,  G06F21/85 ,  H04L63/0227

    Abstract: In described examples, a system on a chip (SoC) and method for sending messages in the SoC include determining locations of initiator-side firewall block and receiver-side firewall block memories using respective pointers to the firewall block memories stored in a single, contiguous memory. Addresses of the pointers within the single memory depend on respective unique firewall identifiers of the firewall blocks. An exclusive security configuration controller uses the pointers to configure the firewall blocks over a security bus which is electrically isolated from a system bus. The system bus is used to send messages from sending functional blocks to receiving functional blocks. The initiator-side firewall block adds a message identifier to messages. The message identifier depends on the initiator-side firewall block's configuration settings. The receiver-side firewall block controls permission for the receiving functional block to access the message, depending on the message identifier and the receiver-side firewall block's configuration settings.

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