公开(公告)号：US20150249654A1

公开(公告)日：2015-09-03

申请号：US14712396

申请日：2015-05-14

Applicant: Texas Instruments Incorporated

Inventor： Amritpal Singh Mundra ,  Denis Roland Beaudoin

IPC: H04L29/06 ,  H04L12/851 ,  H04W12/06

CPC classification number: H04L63/0485 ,  G06F7/588 ,  G06F21/72 ,  G06F2221/2107 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/065 ,  H04L9/0869 ,  H04L9/3013 ,  H04L9/32 ,  H04L9/3236 ,  H04L9/3239 ,  H04L9/3242 ,  H04L47/2441 ,  H04L63/0428 ,  H04L63/08 ,  H04L2209/125 ,  H04L2209/38 ,  H04W12/06

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Abstract translation: 电子电路（200）包括一个或多个可编程控制平面引擎（410,460），其可操作以处理分组标题信息并形成至少一个命令，一个或多个可编程数据平面引擎（310,320,370）选择性地可操作 用于响应于所述至少一个命令可选择的多个密码处理中的至少一个;以及耦合到所述数据平面引擎（310）和所述控制平面引擎（410）的可编程主机处理器（100）。 公开了用于其操作和制造的其他处理器，电路，设备和系统和过程。

公开(公告)号：US20240126560A1

公开(公告)日：2024-04-18

申请号：US18395697

申请日：2023-12-25

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A.T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  G06F13/28 ,  H04L45/00 ,  H04L47/32 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US11726907B2

公开(公告)日：2023-08-15

申请号：US17474141

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

IPC: G11C29/00 ,  G06F12/02 ,  G06F12/0879 ,  G11C11/409 ,  G11C29/42 ,  G06F13/40

CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F12/0879 ,  G06F13/4027 ,  G11C11/409 ,  G11C29/42 ,  G11C29/76

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

公开(公告)号：US20180367516A1

公开(公告)日：2018-12-20

申请号：US16112277

申请日：2018-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Denis Roland Beaudoin

IPC: H04L29/06 ,  H04W12/06 ,  H04L9/32 ,  G06F21/72 ,  H04L9/06 ,  H04L12/851 ,  G06F7/58 ,  H04L9/30 ,  H04L9/08

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

公开(公告)号：US20160173283A1

公开(公告)日：2016-06-16

申请号：US15045948

申请日：2016-02-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Denis Roland Beaudoin

IPC: H04L9/32 ,  H04W12/06 ,  H04L29/06

CPC classification number: H04L63/0485 ,  G06F7/588 ,  G06F21/72 ,  G06F2221/2107 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/065 ,  H04L9/0869 ,  H04L9/3013 ,  H04L9/32 ,  H04L9/3236 ,  H04L9/3239 ,  H04L9/3242 ,  H04L47/2441 ,  H04L63/0428 ,  H04L63/08 ,  H04L2209/125 ,  H04L2209/38 ,  H04W12/06

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

公开(公告)号：US12222390B2

公开(公告)日：2025-02-11

申请号：US18457537

申请日：2023-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Samuel Paul Visalli

IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  H03K19/21

Abstract: A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

公开(公告)号：US12204443B2

公开(公告)日：2025-01-21

申请号：US18449025

申请日：2023-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

IPC: G06F12/02 ,  G06F12/0879 ,  G06F13/40 ,  G11C11/409 ,  G11C29/00 ,  G11C29/42

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

公开(公告)号：US12131504B2

公开(公告)日：2024-10-29

申请号：US17538268

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Mihir Narendra Mody ,  Niraj Nandan ,  Shashank Dabral ,  Rajasekhar Reddy Allu ,  Denis Roland Beaudoin

IPC: G06K9/00 ,  G06T1/20 ,  G06T7/90

CPC classification number: G06T7/90 ,  G06T1/20 ,  G06T2207/10024 ,  G06T2207/20208

Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.

公开(公告)号：US11853772B2

公开(公告)日：2023-12-26

申请号：US17888533

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A. T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US09503265B2

公开(公告)日：2016-11-22

申请号：US15045948

申请日：2016-02-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Denis Roland Beaudoin

IPC: H04L9/32 ,  H04L29/06 ,  H04W12/06

CPC classification number: H04L63/0485 ,  G06F7/588 ,  G06F21/72 ,  G06F2221/2107 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/065 ,  H04L9/0869 ,  H04L9/3013 ,  H04L9/32 ,  H04L9/3236 ,  H04L9/3239 ,  H04L9/3242 ,  H04L47/2441 ,  H04L63/0428 ,  H04L63/08 ,  H04L2209/125 ,  H04L2209/38 ,  H04W12/06

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Abstract translation: 电子电路（200）包括一个或多个可编程控制平面引擎（410,460），其可操作以处理分组标题信息并形成至少一个命令，一个或多个可编程数据平面引擎（310,320,370）选择性地可操作 用于响应于所述至少一个命令可选择的多个密码处理中的至少一个;以及耦合到所述数据平面引擎（310）和所述控制平面引擎（410）的可编程主机处理器（100）。 公开了用于其操作和制造的其他处理器，电路，设备和系统和过程。