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公开(公告)号：US10795685B2
公开(公告)日：2020-10-06
申请号：US16378832
申请日：2019-04-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
IPC: G06F9/38 , G06F11/36 , G06F11/267 , G06F9/30
Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
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公开(公告)号：US10740280B2
公开(公告)日：2020-08-11
申请号：US15714212
申请日：2017-09-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
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公开(公告)号：US10585810B2
公开(公告)日：2020-03-10
申请号：US16019715
申请日：2018-06-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Johann Zipperer
Abstract: A method of protecting software for embedded applications against unauthorized access is disclosed. Software to be protected is loaded into a protected memory area and access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area only either from within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.
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公开(公告)号：US20190303166A1
公开(公告)日：2019-10-03
申请号：US16378832
申请日：2019-04-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Markus Koesler , Johann Zipperer , Christian Wiencke , Wolfgang Lutsch
IPC: G06F9/38 , G06F11/267 , G06F11/36 , G06F9/30
Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
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公开(公告)号：US09952865B2
公开(公告)日：2018-04-24
申请号：US14678944
申请日：2015-04-04
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
CPC classification number: G06F9/3013 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/3877 , G06F9/3889 , G06F13/1678 , G06F13/4018 , G06F13/4022 , Y02D10/14 , Y02D10/151
Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit is coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor is configured to execute instruction words received on the system bus and has a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.
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Patent Agency Ranking
公开(公告)号：US20140089640A1
公开(公告)日：2014-03-27
申请号：US13628366
申请日：2012-09-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Horst Diewald , Johann Zipperer
IPC: G06F9/30
CPC classification number: G06F9/30065 , G06F9/381 , G06F9/3814 , G06F9/3822 , G06F9/3853
Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute, and to enforce atomic execution of the complex instruction during a first-portion of the multiple instruction cycles required to execute the complex instruction. The at least one of the execution units is further configured to enable execution of the complex instruction to be interrupted for execution of a different instruction by the at least one execution unit during execution of a second portion of the multiple instruction cycles. The first portion and the second portion are non-overlapping.
Abstract translation: 处理器包括多个执行单元。 执行单元中的至少一个被配置为执行需要多个指令周期执行的复杂指令，并且在执行复杂指令所需的多个指令周期的第一部分期间执行复指令的原子执行。 所述执行单元中的至少一个还被配置为能够执行要在所述多个指令周期的第二部分的执行期间由所述至少一个执行单元执行不同指令的待中断的所述复杂指令。 第一部分和第二部分是不重叠的。
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公开(公告)号：US11341085B2
公开(公告)日：2022-05-24
申请号：US16920901
申请日：2020-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.
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公开(公告)号：US10928427B2
公开(公告)日：2021-02-23
申请号：US15483625
申请日：2017-04-10
Applicant: Texas Instruments Incorporated
Inventor： Horst Diewald , Johann Zipperer , Peter Weber , Anton Brauchle
IPC: G01R21/127 , G01R15/18
Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.
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公开(公告)号：US10389407B2
公开(公告)日：2019-08-20
申请号：US15816365
申请日：2017-11-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Erich Johann Bayer , Johann Zipperer , Christophe Vaucourt , Tobias Bernhard Fritz
Abstract: In described examples, a system includes a transformer including a primary winding and a secondary winding. The system also includes a primary side circuit coupled to the primary winding of the transformer. The primary side circuit includes a primary controller. The system further includes a secondary side circuit coupled to the secondary winding of the transformer. The primary controller coupled to cause the primary side circuit to transfer power and intermittently transmit data to the secondary side circuit via the primary winding and the secondary winding of the transformer.
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公开(公告)号：US10324116B2
公开(公告)日：2019-06-18
申请号：US14868130
申请日：2015-09-28
Applicant: Texas Instruments Incorporated
Inventor： Horst Diewald , Johann Zipperer , Peter Weber , Anton Brauchle
Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant ON-time.
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