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    Hall sensor using face down structure with through substrate vias
    11.
    发明授权
    Hall sensor using face down structure with through substrate vias 有权

    公开(公告)号：US12259445B2

    公开(公告)日：2025-03-25

    申请号：US18146447

    申请日：2022-12-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daiki Komatsu ,  Masamitsu Matsuura

    IPC: G01R33/07 ,  H10N52/00 ,  H10N52/01

    Abstract: An integrated circuit (IC) package comprises a semiconductor die having a first surface with a Hall-effect sensor circuit and a second surface. A plurality of through substrate vias (TSV) each having a metal layer extend from the first surface of the semiconductor die to the second surface. The IC package includes a portion of a leadframe having a first set of leads and a second set of leads. The first set of leads provide a field generating current path for directing a magnetic field toward the Hall-effect sensor circuit. The second set of leads are attached to bond pads on the semiconductor die. A first side of an insulator is attached to the leadframe using a die attach material, and a second side of the insulator is attached to the first side of the semiconductor die using a bonding material.

    Converter Package with Integrated Inductor
    12.
    发明申请
    Converter Package with Integrated Inductor 有权

    公开(公告)号：US20250046684A1

    公开(公告)日：2025-02-06

    申请号：US18362936

    申请日：2023-07-31

    Applicant: Texas Instruments Incorporated

    Inventor： Makoto Shibuya ,  Yasmine Yan ,  Masamitsu Matsuura ,  Anindya Poddar

    IPC: H01L23/495 ,  H05K1/18

    Abstract: A semiconductor package comprises an integrated circuit die covered by a mold compound to form a four-sided package with a top surface and a bottom surface. A first group of no-lead contacts are exposed on a first side and on the bottom surface of the package. A second group of no-lead contacts are exposed on a second side and on the bottom surface of the package, wherein the second side is opposite the first side. A first external lead extends from a third side of the package. A second external lead extends from a fourth side of the package opposite the third side. The first and second external leads bent to extend above the top surface of the package. The first and second external leads have a gull-wing shape or a J-shape.

    WAFER CHIP SCALE PACKAGE
    17.
    发明申请
    WAFER CHIP SCALE PACKAGE 有权

    公开(公告)号：US20210111136A1

    公开(公告)日：2021-04-15

    申请号：US16739578

    申请日：2020-01-10

    Applicant: Texas Instruments Incorporated

    Inventor： Masamitsu Matsuura ,  Daiki Komatsu

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/528

    Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.

    SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER
    19.
    发明申请
    SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER 有权

    公开(公告)号：US20250112182A1

    公开(公告)日：2025-04-03

    申请号：US18478226

    申请日：2023-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Masamitsu Matsuura ,  Daiki Komatsu ,  Kengo Aoya ,  Ting-Ta Yen

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

    Abstract: A semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. Portions of the semiconductor wafer are covered by a protective overcoat. The semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. The cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulation material overlaying the cap wafer. The insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.

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