公开(公告)号：US11852683B2

公开(公告)日：2023-12-26

申请号：US18155190

申请日：2023-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/31724

Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

公开(公告)号：US11715544B2

公开(公告)日：2023-08-01

申请号：US17538942

申请日：2021-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitesh Mishra ,  Nikita Naresh

IPC: G11C29/20 ,  G11C29/36 ,  G11C29/46 ,  H03K19/173 ,  G11C29/12

CPC classification number: G11C29/36 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/46 ,  H03K19/1737

Abstract: An apparatus includes a first group of memory units and a second group of memory units coupled to a first data path and a second data path coupled to a controller, a first delay element on the first data path coupled to the second group of memory units and configured to send, from the controller to the second group of memory units, signals for write and read operations in a sequence of time cycles delayed by a time cycle with respect to the first group of memory units, and a second delay element on the second data path and coupled to the first group of memory units and configured to send, from the first group of memory units to the controller, test result signals delayed by a time cycle, the delayed test result signals having a matching delay to the delayed write and read operations.

公开(公告)号：US11555853B2

公开(公告)日：2023-01-17

申请号：US17093702

申请日：2020-11-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

Abstract: A system is provided that includes a memory configured to store test patterns. A first lockstep core and a second lockstep core are configured to receive the same set of test patterns. First scan outputs are generated from the first lockstep core, and second scan outputs are generated from the second lockstep core during a reset of the first lockstep core and the second lockstep core. A comparator can be coupled to the first lockstep core and the second lockstep core and is configured to compare the first scan outputs to the second scan outputs. The first and second lockstep cores can be initialized to a similar state if the first and second scan outputs are the same. The first and second lockstep cores can comprise non-resettable flip flops.

公开(公告)号：US11521698B2

公开(公告)日：2022-12-06

申请号：US17002813

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh ,  Prathyusha Teja Inuganti ,  Rakesh Channabasappa Yaraduyathinahalli ,  Aravinda Acharya ,  Jasbir Singh ,  Naveen Ambalametil Narayanan

IPC: G11C29/38 ,  G11C17/00 ,  G11C29/00 ,  G11C11/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/04 ,  G11C29/08 ,  G11C14/00 ,  G06F12/06 ,  G06F9/4401

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

公开(公告)号：US10460821B2

公开(公告)日：2019-10-29

申请号：US15896817

申请日：2018-02-14

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Nikita Naresh ,  Vaskar Sarkar ,  Rajat Mehrotra

IPC: G11C29/12 ,  G11C29/38 ,  G11C29/40 ,  G11C29/04 ,  G11C29/26

Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.