公开(公告)号：US11119909B2

公开(公告)日：2021-09-14

申请号：US16590515

申请日：2019-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

IPC: G11C29/00 ,  G06F12/02 ,  G06F12/0879 ,  G11C11/409 ,  G11C29/42 ,  G06F13/40

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

公开(公告)号：US10853170B2

公开(公告)日：2020-12-01

申请号：US16122939

申请日：2018-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Samuel Paul Visalli

IPC: G06F11/10 ,  G11C29/52

Abstract: A data storage circuit includes memory, an error correcting code (ECC) storage circuit, and control circuitry. The memory is configured to store a data value comprising a plurality of fields. Each of the fields is independently writable. The ECC storage circuit is configured to store an ECC value corresponding to the data value. The control circuitry is configured to receive a field value to be written into one of the fields, and store the field value in the one of the fields by writing only the field value to the memory. The control circuitry is also configured to retrieve the ECC value from the ECC storage circuit, compute an updated ECC value based on the ECC value retrieved from the ECC storage circuit and the field value, and store the updated ECC value in the ECC storage circuit.

公开(公告)号：US12222390B2

公开(公告)日：2025-02-11

申请号：US18457537

申请日：2023-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Samuel Paul Visalli

IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  H03K19/21

Abstract: A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.

公开(公告)号：US12204443B2

公开(公告)日：2025-01-21

申请号：US18449025

申请日：2023-08-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Denis Roland Beaudoin ,  Ritesh Dhirajlal Sojitra ,  Samuel Paul Visalli

IPC: G06F12/02 ,  G06F12/0879 ,  G06F13/40 ,  G11C11/409 ,  G11C29/00 ,  G11C29/42

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

公开(公告)号：US20240027515A1

公开(公告)日：2024-01-25

申请号：US18479177

申请日：2023-10-02

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis Flores ,  Ramakrishnan Venkatasubramanian ,  Samuel Paul Visalli

IPC: G01R31/28 ,  G01R31/40 ,  G06F1/3203

CPC classification number: G01R31/2803 ,  G01R31/40 ,  G06F1/3203

Abstract: In described examples, an SoC includes at least two voltage domains interconnected with a communication bus. Detection logic in a first voltage domain determines when a voltage error occurs in a second voltage domain and isolates communication via the communication bus when a voltage error or a timing error is detected.

公开(公告)号：US11715188B1

公开(公告)日：2023-08-01

申请号：US17682735

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Veeramanikandan Raju ,  Niraj Nandan ,  Samuel Paul Visalli ,  Jason A. T. Jones ,  Kedar Satish Chitnis ,  Gregory Raymond Shurtz ,  Prithvi Shankar Yeyyadi Anantha ,  Sriramakrishnan Govindarajan

IPC: G05B23/02 ,  G06T1/20 ,  G06T7/00 ,  G06T3/40 ,  H04N17/00

CPC classification number: G06T7/0002 ,  G05B23/0259 ,  G06T1/20 ,  G06T3/40 ,  G06T7/97 ,  G06T2207/10016 ,  H04N17/00

Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.

公开(公告)号：US11094392B2

公开(公告)日：2021-08-17

申请号：US16601303

申请日：2019-10-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Charles Lance Fuoco ,  Brian Karguth ,  Jay Bryan Reimer ,  Samuel Paul Visalli

IPC: G11C29/42 ,  G06F9/30 ,  G06F11/10 ,  G11C29/54

Abstract: A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output.