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公开(公告)号：US20220247421A1
公开(公告)日：2022-08-04
申请号：US17588493
申请日：2022-01-31
Applicant: Texas Instruments Incorporated
Inventor： Visvesvaraya Appala Pentakota , Srinivas Kumar Reddy Naru , Chirag Shetty , Eeshan Miglani , Neeraj Shrivastava , Narasimhan Rajagopal , Shagun Dusad
IPC: H03M1/10
Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.
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公开(公告)号：US11239851B2
公开(公告)日：2022-02-01
申请号：US16997975
申请日：2020-08-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinivas Kumar Reddy Naru , Anand Jerry George , Shagun Dusad , Visvesvaraya Appala Pentakota
Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.
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公开(公告)号：US10341082B1
公开(公告)日：2019-07-02
申请号：US15906000
申请日：2018-02-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh Balakrishnan , Shagun Dusad , Visvesvaraya Pentakota , Srinivas Kumar Reddy Naru , Sarma Sundareswara Gunturi , Nagalinga Swamy Basayya Aremallapur
Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.
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公开(公告)号：US10320405B2
公开(公告)日：2019-06-11
申请号：US15909378
申请日：2018-03-01
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
Abstract: In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
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公开(公告)号：US09479186B1
公开(公告)日：2016-10-25
申请号：US14871373
申请日：2015-09-30
Applicant: Texas Instruments Incorporated
CPC classification number: H03M1/0609 , H03M1/203 , H03M1/361
Abstract: In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
Abstract translation: 在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。 主ADC响应于输入信号产生区域信息信号和数字输出。 参考ADC从主ADC接收多个参考电压。 多个参考电压包括第一参考电压和第二参考电压。 参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。 减法器响应于数字输出和参考输出产生一个误差信号。 响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。
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Patent Agency Ranking
公开(公告)号：US20250105854A1
公开(公告)日：2025-03-27
申请号：US18973169
申请日：2024-12-09
Applicant: Texas Instruments Incorporated
Inventor： Visvesvaraya Appala Pentakota , Srinivas Kumar Reddy Naru , Chirag Shetty , Eeshan Miglani , Neeraj Shrivastava , Narasimhan Rajagopal , Shagun Dusad
IPC: H03M1/10
Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.
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公开(公告)号：US20220247420A1
公开(公告)日：2022-08-04
申请号：US17467561
申请日：2021-09-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Narasimhan Rajagopal , Eeshan Miglani , Chirag Chandrahas Shetty , Neeraj Shrivastava , Shagun Dusad , Srinivas Kumar Reddy Naru , Nithin Gopinath , Charls Babu , Shivam Srivastava , Viswanathan Nagarajan , Jagannathan Venkataraman , Harshit Moondra , Prasanth K , Visvesvaraya Appala Pentakota
IPC: H03M1/10
Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
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公开(公告)号：US11309902B2
公开(公告)日：2022-04-19
申请号：US16714835
申请日：2019-12-16
Applicant: Texas Instruments Incorporated
Inventor： Srinivas Kumar Reddy Naru , Narasimhan Rajagopal , Shagun Dusad , Viswanathan Nagarajan , Visvesvaraya Appala Pentakota
Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.
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公开(公告)号：US10419036B2
公开(公告)日：2019-09-17
申请号：US16125826
申请日：2018-09-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.
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公开(公告)号：US10305451B1
公开(公告)日：2019-05-28
申请号：US15839265
申请日：2017-12-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sundarrajan Rangachari , Jaiganesh Balakrishnan , Jawaharlal Tangudu , Srinivas Kumar Reddy Naru
Abstract: In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.
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