公开(公告)号：US20150089293A1

公开(公告)日：2015-03-26

申请号：US14309362

申请日：2014-06-19

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Inventor： Andreas Waechter ,  Mark Jung ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F11/14 ,  G06F9/44 ,  G06F12/02

CPC classification number: G06F11/1417 ,  G06F9/4401 ,  G06F9/4418 ,  G06F11/1469

Abstract: A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.

Abstract translation: 处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。 标准引导顺序用于恢复数据的第一部分。 数据的第二部分与标准引导序列并行地从NVL阵列恢复。 对数据的第二部分执行数据损坏检查。 如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。 如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。 处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。

公开(公告)号：US08854079B2

公开(公告)日：2014-10-07

申请号：US13753856

申请日：2013-01-30

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: H03K19/177 ,  G06F7/00 ,  H03K19/173

CPC classification number: H03K19/173

Abstract: A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.

Abstract translation: 片上系统（SoC）具有耦合到一个或多个核心逻辑块的n行m列的非易失性存储器阵列。 M被限制为奇数。 每次写入一行m个数据位时，使用m个数据位来计算奇偶校验。 在存储奇偶校验位之前，它被反转。 每次读取一行时，检查奇偶校验以确定恢复的数据位中是否存在奇偶校验错误。 当检测到奇偶校验错误时，在SoC上执行引导操作。

公开(公告)号：US20140075218A1

公开(公告)日：2014-03-13

申请号：US13770498

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.

Abstract translation: 计算设备包括与第一功能相关联的第一组非易失性逻辑元件阵列和与第二功能相关联的第二组非易失性逻辑元件阵列。 第一组和第二组非易失性逻辑元件阵列是独立可控的。 第一电源域向计算设备的交换逻辑元件供电，第二电源域为配置成控制用于将数据存储到非易失性逻辑单元阵列或从非易失性逻辑单元阵列读取数据的信号的逻辑元件供电，而第三电源域供电 用于非易失性逻辑元件阵列。 基于系统状态，不同的电源域被独立上电或下电，以减少在冗余逻辑切换期间的功率损耗以及在恢复系统状态期间伴随的寄生功率消耗，并且在计算的常规操作期间减少备用存储元件的功率泄漏 设备。

公开(公告)号：US20140075175A1

公开(公告)日：2014-03-13

申请号：US13770516

申请日：2013-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F9/44

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A device's configuration is controlled through control of its pre-boot process. Protected non-volatile logic element arrays store a machine state configuration of a processing device configured to backup data from volatile storage elements in a plurality of non-volatile logic element arrays. The machine state configuration is read in response to the processing device's entering a pre-boot process. The processing device's configuration is then set to the machine state configuration. This setting of the device configuration can be done by receiving instructions from the protected non-volatile logic element arrays to direct an order in which data for individual device functions are restored from non-volatile logic element arrays in response to the processing device's entering a wakeup or recovery mode. In one approach, the instructions arrange configuration bits that direct operation of a non-volatile logic controller during the wakeup or recovery mode to control the order of data restoration.

Abstract translation: 通过控制其预引导过程来控制设备的配置。 受保护的非易失性逻辑元件阵列存储被配置为从多个非易失性逻辑元件阵列中的易失性存储元件备份数据的处理设备的机器状态配置。 响应于处理设备进入预引导过程，读取机器状态配置。 然后将处理设备的配置设置为机器状态配置。 设备配置的这种设置可以通过从受保护的非易失性逻辑单元阵列接收指令来完成，以指示响应于处理设备进入唤醒而从非易失性逻辑单元阵列恢复各个设备功能的数据的顺序 或恢复模式。 在一种方法中，指令排列在唤醒或恢复模式期间直接操作非易失性逻辑控制器的配置位，以控制数据恢复的顺序。

公开(公告)号：US10902895B2

公开(公告)日：2021-01-26

申请号：US15623441

申请日：2017-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F3/06 ,  G06F11/14 ,  G06F1/32 ,  G06F11/10 ,  G11C14/00 ,  G06F12/02 ,  G06F9/4401 ,  G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  H03K3/3562 ,  G06F13/00

Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

公开(公告)号：US10545728B2

公开(公告)日：2020-01-28

申请号：US15828204

申请日：2017-11-30

Applicant: Texas Instruments Incorporated

Inventor： Sudhanshu Khanna ,  Hao Meng ,  Michael Zwerg ,  Christy Leigh She ,  Steven Craig Bartling

IPC: H03K21/00 ,  G06F7/62 ,  G06F1/26 ,  G08C13/02 ,  H03K5/24 ,  H03K21/40 ,  G11C11/56

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

公开(公告)号：US10468079B2

公开(公告)日：2019-11-05

申请号：US16159433

申请日：2018-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G06F12/02 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

公开(公告)号：US10331203B2

公开(公告)日：2019-06-25

申请号：US15016449

申请日：2016-02-05

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/3293 ,  G06F1/3287 ,  G06F3/06 ,  G06F11/07 ,  G06F1/3206

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

公开(公告)号：US20190043544A1

公开(公告)日：2019-02-07

申请号：US16159433

申请日：2018-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G11C14/00 ,  G06F9/4401 ,  G06F1/32 ,  G06F11/10 ,  G06F12/02 ,  G06F11/14 ,  G06F13/00

Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

公开(公告)号：US09899066B2

公开(公告)日：2018-02-20

申请号：US13770004

申请日：2013-02-19

Applicant: Texas Instruments Incorporated

Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F12/16 ,  G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.