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公开(公告)号：US11615040B2
公开(公告)日：2023-03-28
申请号：US17390428
申请日：2021-07-30
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
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公开(公告)号：US11581897B1
公开(公告)日：2023-02-14
申请号：US17377698
申请日：2021-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Jayawardan Janardhanan , Yogesh Darwhekar
Abstract: A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.
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公开(公告)号：US20230035848A1
公开(公告)日：2023-02-02
申请号：US17390428
申请日：2021-07-30
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
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公开(公告)号：US20220365489A1
公开(公告)日：2022-11-17
申请号：US17317628
申请日：2021-05-11
Applicant: Texas Instruments Incorporated
Inventor： Yogesh Darwhekar , Subhashish Mukherjee , Narala Raghavendra Reddy
Abstract: An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.
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公开(公告)号：US10728068B2
公开(公告)日：2020-07-28
申请号：US15860988
申请日：2018-01-03
Applicant: Texas Instruments Incorporated
IPC: H04L27/22 , H03D3/00 , H03L7/081 , H04L27/227 , H03K19/21 , H03L7/087 , H03L7/113 , H04L7/033 , H04L7/00
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.
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Patent Agency Ranking
公开(公告)号：US20200044605A1
公开(公告)日：2020-02-06
申请号：US16601081
申请日：2019-10-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
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公开(公告)号：US20180183636A1
公开(公告)日：2018-06-28
申请号：US15391675
申请日：2016-12-27
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Yogesh Darwhekar , Subhashish Mukherjee
Abstract: Described examples include a method for operating a receiver including receiving an output of an in-phase IF path; receiving an output of a quadrature IF path; measuring a blocker power on a plurality of IF channels on at least one of the in-phase path and the quadrature path within a fraction of a symbol interval; selecting a selected one of the plurality of IF channels having a low blocker power as an image channel; and providing a local oscillator output to the in-phase IF path and quadrature IF path operate corresponding to the image channel, such that a frequency of the local oscillator output is changed within a fraction of the symbol interval.
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公开(公告)号：US09634736B2
公开(公告)日：2017-04-25
申请号：US15199611
申请日：2016-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Anoop Bhat , Kumar Anurag Shrivastava
CPC classification number: H04B5/0087 , H04B5/0031 , H04L27/04
Abstract: In described examples, a method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially the same resonant frequency, each having antenna coils and switches positioned for changing a Q and a bandwidth of their tank. The antenna coils are separated by a distance that provides near-field communications. The first tank is driven to for generating induced oscillations to transmit a predetermined number of carrier frequency cycles providing data. After the predetermined number of cycles, a switch is activated for widening the bandwidth of the first tank. Responsive to the oscillations in the first tank, the second tank begins induced oscillations. Upon detecting a bit associated with the induced oscillations, a switch is activated for widening the bandwidth of the second tank and a receiver circuit receiving an output of the second tank is reset.
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公开(公告)号：US20160126895A1
公开(公告)日：2016-05-05
申请号：US14529056
申请日：2014-10-30
Applicant: Texas Instruments Incorporated
Inventor： Gireesh Rajendran , Rakesh Kumar , Alok Prakask Joshi , Subhashish Mukherjee , Krishnaswamy Thiagarajan , Apu Sivadas
CPC classification number: H04L27/3405 , H03F1/0227 , H03F3/19 , H03F3/217 , H03F3/245 , H03F2200/331 , H03F2200/336 , H03F2200/451
Abstract: An I converter outputs I sign data and I magnitude data based on received I data. A Q converter outputs Q sign data and Q magnitude data based on received Q data. An I clock generates an I phase based ort the I sign data. A Q clock generates a Q phase based on the Q sign data. An I modulator generates an I magnitude pulse stream based on the I magnitude data. A Q modulator generates a Q magnitude pulse stream based on the Q magnitude data. A digital logic component generates an output signal based on the I phase, the I magnitude pulse stream, the Q phase and the Q magnitude pulse stream. A power amplifier generates an amplified signal based on the output signal.
Abstract translation: I转换器根据接收到的I数据输出I符号数据和I幅度数据。 Q转换器基于接收的Q数据输出Q符号数据和Q幅度数据。 一个I时钟产生一个I相或ort的I符号数据。 Q时钟基于Q符号数据生成Q相。 I调制器基于I幅度数据生成I幅度脉冲流。 Q调制器基于Q幅度数据产生Q幅度脉冲流。 数字逻辑部件基于I相，I幅度脉冲流，Q相和Q幅度脉冲流产生输出信号。 功率放大器基于输出信号产生放大信号。
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公开(公告)号：US20240137031A1
公开(公告)日：2024-04-25
申请号：US18081028
申请日：2022-12-14
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Yogesh Darwhekar
CPC classification number: H03M1/0604 , H03K21/026
Abstract: A digital-to-time converter (DTC) circuit. The DTC circuit includes a charge node. A variable current source has a source input and a source output. The source input is coupled to a DTC digital input and the source output is coupled to the charge node. A capacitor has a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the charge node. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the charge node, the second comparator input is coupled to a reference voltage terminal, and the comparator output is coupled to a DTC output. A pre-charge circuit has a pre-charge control input and a pre-charge output. The pre-charge control input is coupled to a DTC pre-charge input and the pre-charge output is coupled to the capacitor.
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