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公开(公告)号：US11695539B1
公开(公告)日：2023-07-04
申请号：US17587241
申请日：2022-01-28
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Vikram Sharma , Shankar Ramakrishnan , Raghu Ganesan
IPC: H04B1/38 , H04L5/16 , H04L7/033 , H04L7/06 , H04L7/00 , H03K19/173 , H04L7/04 , H03K19/17784
CPC classification number: H04L7/033 , H03K19/1737 , H03K19/17784 , H04L7/0079 , H04L7/0091 , H04L7/048 , H04L7/065
Abstract: A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.
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公开(公告)号：US11637529B2
公开(公告)日：2023-04-25
申请号：US17495097
申请日：2021-10-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumantra Seth , Isha Khandelwal , Rama Santosh Neelim Kumar Kattamuri
Abstract: An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.
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公开(公告)号：US20200321779A1
公开(公告)日：2020-10-08
申请号：US16910656
申请日：2020-06-24
Applicant: Texas Instruments Incorporated
Inventor： Alan Erik Segervall , Ross Anthony Pimentel , Sumantra Seth
Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.
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公开(公告)号：US20190173429A1
公开(公告)日：2019-06-06
申请号：US16225043
申请日：2018-12-19
Applicant: Texas Instruments Incorporated
Inventor： Sumantra Seth , Ashwin Ramachandran , Gururaj Ghorpade
Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.
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公开(公告)号：US09065430B2
公开(公告)日：2015-06-23
申请号：US14258771
申请日：2014-04-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumantra Seth , Somasunder Kattepura Sreenath , Sujoy Chinmoy Chakravarty , Arakali Abhijith
IPC: H03K19/094 , G06F13/20 , H03K3/012 , G06F1/26 , H03K19/0185 , H02J7/00
CPC classification number: H03K3/012 , G06F1/26 , H02J2007/0062 , H03K19/0185
Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.
Abstract translation: 用于确保USB-OTG（On Go Go）会话请求协议的Ultra Deep Sub Micron（UDSM）过程中的VBUS脉冲的架构，该体系结构是至少部署充电电路的类型，其使用连接在 充电电路的前进路径。 该架构可以包括二极管分压器，其包括节点并且在所述充电电路中从VBUS连接。 一个实施例使用包括晶体管的充电和放电电路。 充电电路晶体管可以包括PMOS晶体管，并且放电电路晶体管可以包括NMOS晶体管。 该结构可以包括连接在所述VBUS和地之间的接近100K欧姆的总电阻值的三个电阻串，其中放电电路晶体管可以包括漏极延伸的NMOS晶体管。 充电和放电电路晶体管具有约3.6V的VDS和VGD，由此不需要高VGS晶体管。
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Patent Agency Ranking
公开(公告)号：US12189549B2
公开(公告)日：2025-01-07
申请号：US18126602
申请日：2023-03-27
Applicant: Texas Instruments Incorporated
Inventor： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
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公开(公告)号：US20240297642A1
公开(公告)日：2024-09-05
申请号：US18228570
申请日：2023-07-31
Applicant: Texas Instruments Incorporated
Inventor： Trilok Kamagond , Sumantra Seth
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed corresponding to current limit circuitry with controlled current variation. An example circuit includes a voltage regulator configured to control a first transistor to regulate a supply voltage to a regulated voltage; and current limit circuitry configured to enable a second transistor to lower an output current when a voltage at a control terminal of the first transistor satisfies a threshold.
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公开(公告)号：US20230417529A1
公开(公告)日：2023-12-28
申请号：US18072458
申请日：2022-11-30
Applicant: Texas Instruments Incorporated
Inventor： Raghu Ganesan , Rallabandi Annapurna , Sucheth S. Kuncham , Saravanakkumar Radhakrishnan , Sumantra Seth , Geet Modi
IPC: G01B7/02
CPC classification number: G01B7/026
Abstract: An example first device includes: processor circuitry configured to establish a cable communication; analog to digital converter circuitry configured to sample cable voltages over time; echo estimator circuitry configured to determine a plurality of echo coefficients corresponding to the plurality of voltages; and physical length estimator circuitry configured to: identify a first echo coefficient in the echo coefficients that satisfies a static threshold, the first echo coefficient corresponding to a near end echo; identify a second echo coefficient in the echo coefficients that satisfies a dynamic threshold, the second echo coefficient corresponding to a far end echo; and estimate the length of a cable for the cable communication based on the first echo coefficient and the second echo coefficient.
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公开(公告)号：US11353943B2
公开(公告)日：2022-06-07
申请号：US16799879
申请日：2020-02-25
Applicant: Texas Instruments Incorporated
Inventor： Anurag Arora , Vikram Sharma , Sumantra Seth
IPC: G06F1/32 , G06F1/3209 , G06F1/3234 , G06F1/3287 , G06F1/3296 , G06F1/26
Abstract: A wakeup circuit includes an energy detection circuit and a wakeup signal generation circuit coupled to the energy detection circuit. The energy detection circuit is configured to, in response to receiving an input signal, generate a detect signal that is proportional to the input signal. The energy detection circuit is powered by the input signal. The wakeup signal generation circuit is configured to, in response to receiving the detect signal, generate a wakeup signal.
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公开(公告)号：US11283408B2
公开(公告)日：2022-03-22
申请号：US16225043
申请日：2018-12-19
Applicant: Texas Instruments Incorporated
Inventor： Sumantra Seth , Ashwin Ramachandran , Gururaj Ghorpade
Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.
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