-
公开(公告)号：US11704154B2
公开(公告)日：2023-07-18
申请号：US17359749
申请日：2021-06-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , William Cronin Wallace , Pratheesh Gangadhar Thalakkal Kottilaveedu , David Alston Lide
IPC: G06F9/48 , G06F13/28 , G06F13/40 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00
CPC classification number: G06F9/4881 , G06F1/06 , G06F9/448 , G06F9/5011 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F11/1004 , G06F13/20 , G06F13/28 , G06F13/4068 , G06F16/9035 , H04L1/0041 , G06F2209/503 , G06F2209/5012
Abstract: A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.
-
公开(公告)号：US11290099B2
公开(公告)日：2022-03-29
申请号：US17066660
申请日：2020-10-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , Martin Staebler , William Cronin Wallace
Abstract: An integrated communications subsystem (ICSS) includes a pulse-width modulator which drives a power stage, such as a motor. The pulse-width modulator is configured shut off the power stage when the pulse-width modulator receives a trip signal from a logic circuit of the ICSS. The logic circuit can easily be reprogrammed to send a trip signal only when certain error conditions are detected. Moreover, the ICSS contains one or more filters which can adjust the sensitivity of the logic circuit to error signals, enabling the ICSS to distinguish between true errors which require shutdown and glitches, which can be ignored during operation of the ICSS.
-
公开(公告)号：US10970074B2
公开(公告)日：2021-04-06
申请号：US16424913
申请日：2019-05-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , William Cronin Wallace , David Alston Lide , Pratheesh Gangadhar Thalakkal K{dot over (o)}ttilaveedu
Abstract: A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.
-
公开(公告)号：US10484119B2
公开(公告)日：2019-11-19
申请号：US15712888
申请日：2017-09-22
Applicant: Texas Instruments Incorporated
Inventor： Thomas Anton Leyrer , Thomas Mauer
IPC: H04L12/64 , H04J3/06 , H04L12/861 , H04L29/06 , H04L12/403 , H04L12/863
Abstract: A real-time Ethernet (RTE) protocol includes start-up frames originated by a master device for network initialization including a preamble, destination address (DA), source address (SA), a type field, and a status field including state information that indicates a current protocol state that the Ethernet network is in for the slave devices to translate for dynamically switching to one of a plurality of provided frame forwarding modes. The start-up frames include device Discovery frames at power up, Parameterization frames that distribute network parameters, and Time Synchronization frames including the master's time and unique assigned communication time slots for each slave device. After the initialization at least one data exchange frame is transmitted exclusive of SA and DA including a preamble that comprises a header that differentiates between master and slave, a type field, a status field excluding the current protocol state, and a data payload.
-
15.发明授权公开(公告)号：US12113612B2
公开(公告)日：2024-10-08
申请号：US17876662
申请日：2022-07-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Chunhua Hu , Venkateswar Reddy Kowkutla , Eric Hansen , Denis Beaudoin , Thomas Anton Leyrer
CPC classification number: H04J3/0658 , H04J3/0641 , H04J3/0676 , H04J3/0679 , H04J3/0691 , H04J3/0667 , H04J3/0688 , H04L7/0083
Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.
-
Patent Agency Ranking
16.发明授权公开(公告)号：US11343205B2
公开(公告)日：2022-05-24
申请号：US16425734
申请日：2019-05-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: H04L49/25 , G05B19/4155 , H04L43/16 , H04L45/74 , H04L47/32
Abstract: An ultra-high speed electronic communications device includes: a network communications interface; a memory; and one or more processing units, communicatively coupled to the memory and the network communications interface, wherein the memory stores instructions configured to cause the one or more processing units to: receive a data packet using the network communications interface; determine a classification of the data packet based, at least in part, on a plurality of factors, wherein the plurality of factors comprises a rate at which the data packet was received and a time at which the data packet was received; select, based at least in part, on the classification, an operation from a plurality of operations, wherein the plurality of operations comprises a cut-through operation and a store-and-forward operation; and perform the selected operation.
-
公开(公告)号：US11281493B2
公开(公告)日：2022-03-22
申请号：US16424648
申请日：2019-05-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , William Cronin Wallace
IPC: G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , G06F11/10 , H04L1/00 , G06F13/28 , G06F13/40
Abstract: A task manager tightly coupled to a programmable real-time unit (PRU), the task manager configured to: detect a first event; assert, a request to the PRU during a first clock cycle that the PRU perform a second task; receive an acknowledgement of the request from the PRU during the first clock cycle; save a first address in a memory during the first clock cycle of the PRU, the first address corresponding to a first task of the PRU, the first address present in a current program counter of the PRU; load a second address of the memory into a second program counter during the first clock cycle, the second address corresponding to the second task; and load, during a second clock cycle, the second address into the current program counter, wherein the second clock cycle immediately follows the first clock cycle.
-
公开(公告)号：US11243809B2
公开(公告)日：2022-02-08
申请号：US17126143
申请日：2020-12-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , William Cronin Wallace , David Alston Lide
IPC: G06F11/10 , G06F9/48 , G06F16/9035 , G06F9/52 , G06F9/50 , G06F1/06 , G06F13/20 , G06F9/448 , H04L1/00 , G06F13/28 , G06F13/40
Abstract: A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
-
公开(公告)号：US20200304611A1
公开(公告)日：2020-09-24
申请号：US16820440
申请日：2020-03-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , Peter Aberl
Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method comprises sampling a first data interface to generate a first data sample. The method further comprises sampling a second data interface to generate a second data sample. The method further comprises combining the first data sample and the second data sample to generate combined data. The method further comprises transmitting the combined data on a sample basis at an Ethernet physical layer of communication.
-
公开(公告)号：US20200014479A1
公开(公告)日：2020-01-09
申请号：US16576212
申请日：2019-09-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Anton Leyrer , Thomas Mauer
IPC: H04J3/06 , H04L12/861 , H04L12/64 , H04L29/06
Abstract: A real-time Ethernet (RTE) protocol includes start-up frames originated by a master device for network initialization including a preamble, destination address (DA), source address (SA), a type field, and a status field including state information that indicates a current protocol state that the Ethernet network is in for the slave devices to translate for dynamically switching to one of a plurality of provided frame forwarding modes. The start-up frames include device Discovery frames at power up, Parameterization frames that distribute network parameters, and Time Synchronization frames including the master's time and unique assigned communication time slots for each slave device. After the initialization at least one data exchange frame is transmitted exclusive of SA and DA including a preamble that comprises a header that differentiates between master and slave, a type field, a status field excluding the current protocol state, and a data payload.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.023 seconds)
