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    Metal loss prevention in conductive structures
    11.
    发明授权
    Metal loss prevention in conductive structures 有权

    公开(公告)号：US11631640B2

    公开(公告)日：2023-04-18

    申请号：US17675302

    申请日：2022-02-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L23/532

    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

    Novel Structures for Tuning Threshold Voltage
    12.
    发明申请
    Novel Structures for Tuning Threshold Voltage 有权

    公开(公告)号：US20210242092A1

    公开(公告)日：2021-08-05

    申请号：US16925893

    申请日：2020-07-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78

    Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

    MULTI-FUNCTIONAL SHUTTER DISK FOR THIN FILM DEPOSITION CHAMBER
    13.
    发明申请
    MULTI-FUNCTIONAL SHUTTER DISK FOR THIN FILM DEPOSITION CHAMBER 有权

    公开(公告)号：US20210115554A1

    公开(公告)日：2021-04-22

    申请号：US16657832

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Yi-Ming Dai

    IPC: C23C16/02 ,  C23C16/458 ,  C23C16/34 ,  C23C14/02 ,  C23C16/46 ,  C23C14/34

    Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

    Threshold Voltage Tuning For Fin-Based Integrated Circuit Device
    15.
    发明申请
    Threshold Voltage Tuning For Fin-Based Integrated Circuit Device 审中-公开

    公开(公告)号：US20190139954A1

    公开(公告)日：2019-05-09

    申请号：US15808285

    申请日：2017-11-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L27/088 ,  H01L21/02 ,  H01L21/3213

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

    Method for fabricating semiconductor structure, and solid precursor delivery system
    17.
    发明授权
    Method for fabricating semiconductor structure, and solid precursor delivery system 有权
    半导体结构的制造方法和固体前驱体输送系统

    公开(公告)号：US09343315B2

    公开(公告)日：2016-05-17

    申请号：US14092362

    申请日：2013-11-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Liang Cheng ,  Chien-Hao Tseng ,  Yen-Yu Chen ,  Ching-Chia Wu ,  Chang-Sheng Lee ,  Wei Zhang

    IPC: H01L21/469 ,  H01L21/28 ,  C23C16/44 ,  C23C16/448

    CPC classification number: C23C16/4402 ,  C23C16/4481 ,  C23C16/4485 ,  C23C16/45544 ,  C23C16/45553 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28185 ,  H01L29/517

    Abstract: A method for fabricating a semiconductor structure is provided, including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film. A method for modifying a resistance film source in a semiconductor fabrication and a solid precursor delivery system are also provided. The method for fabricating a semiconductor structure in the present disclosure can remove small particles or ultra-small particles from solid precursor, and does not need extra time to dump cracked solid precursor.

    Abstract translation: 提供一种制造半导体结构的方法，包括：提供具有第一平均粒度的固体前体; 将有机溶剂中的固体前体溶解成中间体; 使中间体重结晶形成固体颗粒，其中固体颗粒具有大于第一平均粒度的第二平均粒径; 蒸发固体颗粒以形成成膜气体; 并将成膜气体沉积在基板上以形成电阻膜。 还提供了一种用于修改半导体制造中的电阻膜源和固体前体输送系统的方法。 在本发明中制造半导体结构的方法可以从固体前驱物除去小颗粒或超小颗粒，并且不需要额外的时间来倾倒破裂的固体前体。

    Apparatus and System for Preventing Backside Peeling Defects on Semiconductor Wafers
    18.
    发明申请
    Apparatus and System for Preventing Backside Peeling Defects on Semiconductor Wafers 审中-公开
    用于防止半导体晶片背面剥离缺陷的装置和系统

    公开(公告)号：US20150000599A1

    公开(公告)日：2015-01-01

    申请号：US13929297

    申请日：2013-06-27

    Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

    Inventor： Yen-Yu Chen ,  Wei-Jen Chen ,  Yi-Chen Chiang ,  Tsang-Yang Liu ,  Chang-Sheng Lee ,  Wei-Chen Liao ,  Wei Zhang

    IPC: H01L21/02

    CPC classification number: H01L21/68742

    Abstract: A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.

    Abstract translation: 一种装置包括基座和非反应性气体源。 基座具有通孔和晶片支撑表面。 每个通孔包括升降销和升降销头。 提升销在通孔中具有垂直的运动程度以提升或将基片放置在基座上。 提升销头具有至少一个流动通道结构，其从其第一表面延伸，至少部分地暴露于基座的底侧，其第二表面暴露于基座的顶侧，其中提升销。 非反应性气体源构造成通过流道结构通过基座的底侧将气体流动到晶片的背面。

    Deposition system and method
    20.
    发明授权
    Deposition system and method 有权

    公开(公告)号：US12198927B2

    公开(公告)日：2025-01-14

    申请号：US17461725

    申请日：2021-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Hsi Wang ,  Yen-Yu Chen

    IPC: C23C14/34 ,  C23C14/35 ,  C23C14/54 ,  H01J37/34 ,  H01L21/02 ,  H01L21/67 ,  H01L21/66

    Abstract: A deposition system is provided capable of extending the chamber running time by preventing the target and other components from deformation due to thermal stress from the sputtering process by maintaining the temperature within the predetermined temperature range. The deposition system includes a substrate process chamber, a target within the substrate process chamber, and a plurality of grooves formed on the target in a circular formation. The plurality of grooves includes a first groove on a center portion of the target and a second groove on a periphery portion of the target.

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