公开(公告)号：US11694955B2

公开(公告)日：2023-07-04

申请号：US17226963

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Sheng Zheng ,  Chih-Lin Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/5329 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device comprises a first dielectric layer, a first conductor, a carbon-containing etch stop layer, a second dielectric layer, and a second conductor. The first conductor has a lower portion in the first dielectric layer. The carbon-containing etch stop layer wraps an upper portion of the first conductor. The second dielectric layer is over the carbon-containing etch stop layer. An interface formed by the second dielectric layer and the carbon-containing etch stop layer is higher over the first conductor than over the first dielectric layer. The second conductor is in the second dielectric layer.

公开(公告)号：US11362089B2

公开(公告)日：2022-06-14

申请号：US16730271

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Cheng-Wei Lian

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor structures and method for forming the same are provided. The method for manufacturing the semiconductor structure includes forming a first gate dielectric layer over a substrate and forming a first capping layer over the first gate dielectric layer. The method for manufacturing the semiconductor structure includes oxidizing the first capping layer to form a first capping oxide layer and forming a first work function metal layer over the first capping oxide layer. The method for manufacturing the semiconductor structure includes forming a first gate electrode layer over the first work function metal layer.

公开(公告)号：US11063039B2

公开(公告)日：2021-07-13

申请号：US16048744

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cong-Min Fang ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

公开(公告)号：US11056384B2

公开(公告)日：2021-07-06

申请号：US16678666

申请日：2019-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia Hsieh ,  Long-Jie Hong ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/768 ,  H01L29/16 ,  H01L29/161 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L23/485 ,  H01L21/8238 ,  H01L29/165 ,  H01L23/532

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US10043802B2

公开(公告)日：2018-08-07

申请号：US14689859

申请日：2015-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Cheng-Wei Lian

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8238

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The gate structure includes a gate dielectric layer formed over the substrate and a capping layer formed over the gate dielectric layer. The gate structure further includes a capping oxide layer formed over the capping layer and a work function metal layer formed over the capping oxide layer. The gate structure further includes a gate electrode layer formed over the work function metal layer.

公开(公告)号：US09941152B2

公开(公告)日：2018-04-10

申请号：US15425639

申请日：2017-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wen-Jia Hsieh ,  Chih-Lin Wang ,  Chia-Der Chang

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/76814 ,  H01L21/02244 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.

公开(公告)号：US09837487B2

公开(公告)日：2017-12-05

申请号：US14954524

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US09633941B2

公开(公告)日：2017-04-25

申请号：US14832655

申请日：2015-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Cheng Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/76877 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.

公开(公告)号：US20230378253A1

公开(公告)日：2023-11-23

申请号：US18358399

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L29/7848 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20230178475A1

公开(公告)日：2023-06-08

申请号：US17832489

申请日：2022-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun HE ,  Li-Hsien Huang ,  Yao-Chun Chuang ,  Chih-Lin Wang ,  Shih-Kang Tien

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L21/823475 ,  H01L21/823431 ,  H01L25/105

Abstract: A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third lane region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.