公开(公告)号：US20140347110A1

公开(公告)日：2014-11-27

申请号：US14456064

申请日：2014-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN ,  Tao Wen CHUNG ,  Ming-Chieh HUANG ,  Chih-Chang LIN ,  Tsung-Ching HUANG ,  Fu-Lung HSUEH

IPC: H03L7/10 ,  H03L7/107 ,  H03L7/097

CPC classification number: H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20230400647A1

公开(公告)日：2023-12-14

申请号：US18232342

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN ,  Min-Hsiang HSU

IPC: G02B6/42

CPC classification number: G02B6/4215 ,  G02B6/4206

Abstract: Disclosed are apparatus and methods for optical coupling in optical communications. In one embodiment, an apparatus for optical coupling is disclosed. The apparatus includes: a planar layer; an array of scattering elements arranged in the planar layer at a plurality of intersections of a first set of concentric elliptical curves crossing with a second set of concentric elliptical curves rotated proximately 90 degrees to form a two-dimensional (2D) grating; a first taper structure formed in the planar layer connecting a first convex side of the 2D grating to a first waveguide; and a second taper structure formed in the planar layer connecting a second convex side of the 2D grating to a second waveguide. Each scattering element is a pillar into the planar layer. The pillar has a top surface whose shape is a concave polygon having at least 6 corners.

公开(公告)号：US20230290782A1

公开(公告)日：2023-09-14

申请号：US18198195

申请日：2023-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN

IPC: H01L27/095 ,  H01L29/20 ,  H01L29/778 ,  H01L29/49 ,  H01L29/205 ,  H01L21/8252 ,  H01L21/02 ,  H03K17/16 ,  H01L29/66

CPC classification number: H01L27/095 ,  H01L21/0254 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4958 ,  H01L29/66462 ,  H01L29/7787 ,  H03K17/161 ,  H01L29/42316

Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

公开(公告)号：US20230121421A1

公开(公告)日：2023-04-20

申请号：US18081525

申请日：2022-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN ,  Min-Hsiang HSU

IPC: G02B6/42

Abstract: Disclosed are apparatus and methods for optical coupling in optical communications. In one embodiment, an apparatus for optical coupling is disclosed. The apparatus includes: a planar layer; an array of scattering elements arranged in the planar layer at a plurality of intersections of a first set of concentric elliptical curves crossing with a second set of concentric elliptical curves rotated proximately 90 degrees to form a two-dimensional (2D) grating; a first taper structure formed in the planar layer connecting a first convex side of the 2D grating to a first waveguide; and a second taper structure formed in the planar layer connecting a second convex side of the 2D grating to a second waveguide. Each scattering element is a pillar into the planar layer. The pillar has a top surface whose shape is a concave polygon having at least 6 corners.

公开(公告)号：US20220130989A1

公开(公告)日：2022-04-28

申请号：US17571281

申请日：2022-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN

IPC: H01L29/778 ,  H01L27/085 ,  H01L29/66 ,  H01L29/205

Abstract: Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.

公开(公告)号：US20220099726A1

公开(公告)日：2022-03-31

申请号：US17039627

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ann LAI ,  Ruo-Rung HUANG ,  Kun-Lung CHEN ,  Chun-Yi YANG ,  Chan-Hong CHERN

IPC: G01R31/26 ,  H03K17/687 ,  H03K3/017 ,  G01R31/27

Abstract: An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

公开(公告)号：US20210280580A1

公开(公告)日：2021-09-09

申请号：US17330851

申请日：2021-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN

IPC: H01L27/088 ,  H01L29/778 ,  H03K17/687 ,  H01L21/8252 ,  H01L29/43 ,  H01L29/66

Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.

公开(公告)号：US20200161463A1

公开(公告)日：2020-05-21

申请号：US16601790

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chan-Hong CHERN

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L27/085

Abstract: Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.

公开(公告)号：US20250063824A1

公开(公告)日：2025-02-20

申请号：US18450475

申请日：2023-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Shih-Fan CHEN ,  Sheng-Fu HSU ,  Yi-An LAI ,  Chan-Hong CHERN ,  Cheng-Hsiang HSIEH

IPC: H01L27/02 ,  H02H9/04

Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

公开(公告)号：US20240377590A1

公开(公告)日：2024-11-14

申请号：US18784541

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Hsiang HSU ,  Chewn-Pu JOU ,  Chan-Hong CHERN ,  Cheng-Tse TANG ,  Yung-Jr HUNG ,  Lan-Chou CHO

IPC: G02B6/30

Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.