公开(公告)号：US20250060534A1

公开(公告)日：2025-02-20

申请号：US18451984

申请日：2023-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Chih-Hao Yu ,  Ren-Fen Tsui ,  Jui Lin Chao

IPC: G02B6/293 ,  G02B6/12

Abstract: Optical devices and methods of manufacture are presented in which a resonant ring is incorporated with a optical device on an interposer substrate. The material for the resonant ring may be a material that can trigger second order non-linearity in received light or a material that can trigger third order non-linearity without electrical driving mechanisms.

公开(公告)号：US20240379364A1

公开(公告)日：2024-11-14

申请号：US18779365

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US20240319590A1

公开(公告)日：2024-09-26

申请号：US18186413

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Yu-Yi Huang ,  Chih-Hao Yu ,  Yu-Ting Yen ,  Shih-Peng Tai

IPC: G03F7/00 ,  G03F7/075 ,  G03F7/09 ,  G03F7/16

CPC classification number: G03F7/0005 ,  G03F7/0757 ,  G03F7/091 ,  G03F7/167 ,  G03F7/7015

Abstract: Optical devices and methods of manufacture are presented in which a first mask is utilized for multiple purposes. Some methods include depositing a first mask over a support material, forming a concave surface in the support material through the first mask, and bonding the first mask to a first bonding layer over an optical interposer.

公开(公告)号：US20230335620A1

公开(公告)日：2023-10-19

申请号：US18336788

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/7853 ,  H01L21/0214

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US20220351975A1

公开(公告)日：2022-11-03

申请号：US17863006

申请日：2022-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US20250149388A1

公开(公告)日：2025-05-08

申请号：US19019077

申请日：2025-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Hsiu-Hao Tsao ,  Chih-Hao Yu ,  Yu-Jiun Peng ,  Chang-Yun Chang

IPC: H01L21/66 ,  H10D30/01 ,  H10D64/01 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03

Abstract: A system includes a gate formation tool configured to form a sacrificial gate structure and a replacement gate structure, a device dimension measuring tool configured to measure a dimension of the sacrificial gate structure, and a determination unit configured to pick an etching recipe from a series of etching recipes based on the measured dimension of the sacrificial gate structure. The gate formation tool is also configured to partially remove the sacrificial gate structure using the picked etching recipe to form a gate trench for filling the replacement gate structure therein. A portion of the sacrificial gate structure remains in the gate trench, and the series of etching recipes differ at least in a size of the remaining portion of the sacrificial gate structure.

公开(公告)号：US12087842B2

公开(公告)日：2024-09-10

申请号：US18336788

申请日：2023-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/7853 ,  H01L21/0214 ,  H01L21/0228

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US20240103218A1

公开(公告)日：2024-03-28

申请号：US18153661

申请日：2023-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Jui Lin Chao ,  Chen-Hua Yu ,  Chih-Hao Yu ,  Shih-Peng Tai

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13 ,  G02B2006/12121

Abstract: Optical devices and methods of manufacture are presented in which a laser die or other heterogeneous device is embedded within an optical device and evanescently coupled to other devices. The evanescent coupling can be performed either from the laser die to a waveguide, to an external cavity, to an external coupler, or to an interposer substrate.

公开(公告)号：US20220223718A1

公开(公告)日：2022-07-14

申请号：US17706296

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bone-Fong Wu ,  Chih-Hao Yu ,  Chia-Pin Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

公开(公告)号：US20210183713A1

公开(公告)日：2021-06-17

申请号：US17075313

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.