中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

88 records (took 0.027 seconds)

    High Electron Mobility Transistors
    11.
    发明申请
    High Electron Mobility Transistors 有权
    高电子迁移率晶体管

    公开(公告)号：US20140203289A1

    公开(公告)日：2014-07-24

    申请号：US13745925

    申请日：2013-01-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/66

    CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

    Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

    Abstract translation: 本公开涉及双层AlGaN的施主层和在高电子迁移率晶体管（HEMT）内的相关制造方法，其被配置为提供低电阻欧姆源极和漏极触点以降低功耗，同时保持高的迁移率 在HEMT的通道内的二维电子气（2DEG）。 双层AlGaN的施主层包括位于迁移率增强层上的Al x Ga（1-x）N的电阻减小层AlzGa（1-z）N的迁移率增强层，其中欧姆源和漏极 触点连接到HEMT。 移动性增强层下方设置沟道层，其中2DEG驻留，形成HEMT的沟道。

    Source/Drains In Semiconductor Devices and Methods of Forming Thereof
    12.
    发明公开
    Source/Drains In Semiconductor Devices and Methods of Forming Thereof 审中-公开

    公开(公告)号：US20230378297A1

    公开(公告)日：2023-11-23

    申请号：US18366956

    申请日：2023-08-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Kuei-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

    IPC: H01L29/423 ,  H01L29/78 ,  H01L29/788

    CPC classification number: H01L29/42384 ,  H01L29/785 ,  H01L29/7889

    Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

    VOLTAGE BREAKDOWN UNIFORMITY IN PIEZOELECTRIC STRUCTURE FOR PIEZOELECTRIC DEVICES
    15.
    发明申请
    VOLTAGE BREAKDOWN UNIFORMITY IN PIEZOELECTRIC STRUCTURE FOR PIEZOELECTRIC DEVICES 有权

    公开(公告)号：US20220344575A1

    公开(公告)日：2022-10-27

    申请号：US17241620

    申请日：2021-04-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Chiao-Chun Hsu ,  Chung-Yi Yu

    IPC: H01L41/273 ,  C23C16/458 ,  C23C16/46 ,  H01L41/297 ,  H01L41/318

    Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.

    High electron mobility transistors
    16.
    发明授权
    High electron mobility transistors 有权

    公开(公告)号：US10991819B2

    公开(公告)日：2021-04-27

    申请号：US16132793

    申请日：2018-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/43

    Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

    DOPED BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON
    17.
    发明申请
    DOPED BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON 审中-公开

    公开(公告)号：US20200075314A1

    公开(公告)日：2020-03-05

    申请号：US16395673

    申请日：2019-04-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Kuei-Ming Chen

    IPC: H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L23/00 ,  H01L29/66

    Abstract: Various embodiments of the present application are directed towards a group III-V device including a seed buffer layer that is doped and that is directly on a silicon substrate. In some embodiments, the group III-V device includes the silicon substrate, the seed buffer layer, a heterojunction structure, a pair of source/drain electrodes, and a gate electrode. The seed buffer layer overlies and directly contacts the silicon substrate. Further, the seed buffer layer includes a group III nitride (e.g., AlN) that is doped with p-type dopants. The heterojunction structure overlies the seed buffer layer. The source/drain electrodes overlie the heterojunction structure. The gate electrode overlies the heterojunction structure, laterally between the source/drain electrodes. The p-type dopants prevent the formation of a two-dimensional hole gas (2DHG) in the silicon substrate, along an interface at which the silicon substrate and the seed buffer layer directly contact.

Patent Agency Ranking