公开(公告)号：US20210328018A1

公开(公告)日：2021-10-21

申请号：US17360451

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

公开(公告)号：US11145653B2

公开(公告)日：2021-10-12

申请号：US16585267

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor device that includes a semiconductor device that includes a first transistor having a first gate structure. The first gate structure includes a first gate dielectric layer doped with a first dopant at a first dopant concentration and a first work function layer on the first gate dielectric layer. The first gate structure also includes a first gate electrode on the first work function layer. The semiconductor device also includes a second transistor having a second gate structure, where the second gate structure includes a second gate dielectric layer doped with a second dopant at a second dopant concentration lower than the first dopant concentration. The second gate structure also includes a second work function layer on the second gate dielectric layer and a second gate electrode on the second work function layer.

公开(公告)号：US11018022B2

公开(公告)日：2021-05-25

申请号：US16035159

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Ming Chang ,  Chih-Cheng Lin ,  Chi-Ying Wu ,  Wei-Ming You ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L21/335 ,  H01L21/8232 ,  H01L21/425 ,  H01L21/322 ,  H01L21/28 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes depositing a gate dielectric layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the gate dielectric layer is over the first fin portion. The method includes forming a gate electrode layer over the gate dielectric layer. The gate electrode layer includes fluorine. The method includes annealing the gate electrode layer and the gate dielectric layer so that fluorine from the gate electrode layer diffuses into the gate dielectric layer.

公开(公告)号：US20240177996A1

公开(公告)日：2024-05-30

申请号：US18412173

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Mao-Lin Huang ,  Lung-Kun Chu ,  Huang-Lin Chao ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/28158 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553

Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive

公开(公告)号：US11901450B2

公开(公告)日：2024-02-13

申请号：US17362317

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/0234 ,  H01L21/02181 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US11871581B2

公开(公告)日：2024-01-09

申请号：US17472479

申请日：2021-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Huang-Lin Chao

IPC: H10B53/20 ,  H01L29/423 ,  H10B51/20 ,  H10B53/00 ,  H01L23/528 ,  H01L23/522 ,  H10B51/10 ,  H10B53/10

CPC classification number: H10B53/20 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/42392 ,  H10B51/10 ,  H10B51/20 ,  H10B53/00 ,  H10B53/10

Abstract: A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

公开(公告)号：US20230356356A1

公开(公告)日：2023-11-09

申请号：US18355884

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hung Liao ,  Chen-Hao Wu ,  An-Hsuan Lee ,  Huang-Lin Chao

IPC: B24B53/017 ,  B24B57/02

CPC classification number: B24B53/017 ,  B24B57/02

Abstract: The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

公开(公告)号：US20230058800A1

公开(公告)日：2023-02-23

申请号：US17982028

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Hsuan Lee ,  Chun-Hung Liao ,  Chen-Hao Wu ,  Shen-Nan Lee ,  Teng-Chun Tsai ,  Huang-Lin Chao

IPC: H01L21/321 ,  C09G1/02 ,  H01L21/768

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

公开(公告)号：US20230009485A1

公开(公告)日：2023-01-12

申请号：US17651869

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Hsiang-Pi Chang ,  Huang-Lin Chao ,  Chung-Liang Cheng ,  Chi On Chui ,  Kun-Yu Lee ,  Tzer-Min Shen ,  Yen-Tien Tung ,  Chun-I Wu

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/324

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

公开(公告)号：US20220254684A1

公开(公告)日：2022-08-11

申请号：US17519242

申请日：2021-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peng-Soon LIM ,  Chung-Liang Cheng ,  Huang-Lin Chao

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522

Abstract: A semiconductor device with liner-free contact structures and a method of fabricating the same are disclosed. The method includes forming first and second source/drain (S/D) regions on first and second fin structures, forming a first dielectric layer between the first and second S/D regions, forming first and second gate-all-around (GAA) structures on the first and second fin structures, forming a second dielectric layer on the first and second GAA structures and the first dielectric layer, forming a tapered trench opening in the second dielectric layer and on the first and second GAA structures and the first dielectric layer, selectively forming a seed layer on top surfaces of the first and second GAA structures and the first dielectric layer that are exposed in the tapered trench opening, and selectively depositing a conductive layer on the seed layer to fill the tapered trench opening.