公开(公告)号：US10121812B2

公开(公告)日：2018-11-06

申请号：US15365064

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang ,  Wei-Chih Weng ,  Yu-Yang Shen

IPC: H01L21/78 ,  H01L27/146 ,  H01L23/528 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/532

Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.

公开(公告)号：US20170186799A1

公开(公告)日：2017-06-29

申请号：US15365064

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang ,  Wei-Chih Weng ,  Yu-Yang Shen

IPC: H01L27/146 ,  H01L25/00 ,  H01L25/065 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L27/14634 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1469

Abstract: The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.

公开(公告)号：US09318526B2

公开(公告)日：2016-04-19

申请号：US14822575

申请日：2015-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC: H01L21/00 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/18

Abstract: A method for fabricating an image-sensor device is provided. The method includes forming a radiation-sensing region and a doped isolation region in a semiconductor substrate. The doped isolation region is adjacent to the radiation-sensing region. The method also includes thinning the semiconductor substrate such that the radiation-sensing region and the doped isolation region are exposed. The method further includes partially removing the doped isolation region to form a recess. In addition, the method includes forming a negatively charged film over an interior surface of the recess and a surface of the radiation-sensing exposed after the thinning of the semiconductor substrate.

Abstract translation: 提供了一种用于制造图像传感器装置的方法。 该方法包括在半导体衬底中形成辐射感测区域和掺杂隔离区域。 掺杂隔离区域与辐射感测区域相邻。 该方法还包括使半导体衬底变薄从而暴露辐射感测区域和掺杂隔离区域。 该方法还包括部分去除掺杂隔离区以形成凹陷。 此外，该方法包括在凹部的内表面上形成带负电荷的膜以及在半导体衬底变薄之后暴露的辐射敏感表面。

公开(公告)号：US09136298B2

公开(公告)日：2015-09-15

申请号：US14016949

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung

IPC: H01L31/0232 ,  H01L27/146 ,  H01L31/18

CPC classification number: H01L27/1463 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L31/18

Abstract: Embodiments of mechanisms of for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region operable to detect incident radiation that enters the substrate through the back surface. The image-sensor device further includes a doped isolation region formed in the substrate and adjacent to the radiation-sensing region. In addition, the image-sensor device includes a deep-trench isolation structure formed in the doped isolation region. The deep-trench isolation structure includes a trench extending from the back surface and a negatively charged film covering the trench.

Abstract translation: 提供了用于形成图像传感器装置的机构的实施例。 图像传感器装置包括具有前表面和后表面的基板。 图像传感器装置还包括可操作以检测通过后表面进入衬底的入射辐射的辐射感测区域。 图像传感器装置还包括形成在衬底中并且与辐射感测区域相邻的掺杂隔离区域。 此外，图像传感器装置包括在掺杂隔离区域中形成的深沟槽隔离结构。 深沟槽隔离结构包括从后表面延伸的沟槽和覆盖沟槽的带负电的膜。

公开(公告)号：US11694979B2

公开(公告)日：2023-07-04

申请号：US17236360

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sin-Yao Huang ,  Jeng-Shyan Lin ,  Shih-Pei Chou ,  Tzu-Hsuan Hsu

IPC: H01L23/00 ,  H01L27/146

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L27/1464 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14689

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first isolation structure on a first surface of a substrate. A second isolation structure is formed into the first surface of the substrate. Sidewalls of the first isolation structure are disposed laterally between inner sidewalls of the second isolation structure. A bond pad is formed in the substrate such that the second isolation structure continuously laterally wraps around the bond pad.

公开(公告)号：US11018177B2

公开(公告)日：2021-05-25

申请号：US16556654

申请日：2019-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Shyan Lin ,  Shu-Ting Tsai ,  Tzu-Hsuan Hsu

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a photodetector disposed in a semiconductor substrate. An interlayer dielectric (ILD) structure is disposed on a first side of the semiconductor substrate. A storage node is disposed in the semiconductor substrate and spaced from the photodetector, where the storage node is spaced from the first side by a first distance. A first isolation structure is disposed in the semiconductor substrate and between the photodetector and the storage node, where the first isolation structure extends into the semiconductor substrate from a second side of the semiconductor substrate that is opposite the first side, and where the first isolation structure is spaced from the first side by a second distance that is less than the first distance.

公开(公告)号：US20190244999A1

公开(公告)日：2019-08-08

申请号：US16388071

申请日：2019-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Chun-Chieh Chuang ,  Jeng-Shyan Lin

IPC: H01L27/146 ,  H01L23/48

CPC classification number: H01L27/14636 ,  H01L23/481 ,  H01L27/14621 ,  H01L27/1464 ,  H01L27/14683

Abstract: An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.

公开(公告)号：US10163973B2

公开(公告)日：2018-12-25

申请号：US15461719

申请日：2017-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Kuei Chang ,  Keng-Yu Chou ,  Jen-Cheng Liu ,  Jeng-Shyan Lin

IPC: H01L27/146 ,  G02B6/43 ,  G02B6/42

Abstract: A method for forming an FSI image sensor device structure is provided. The method includes forming a pixel region in a substrate and forming a dielectric layer over the substrate. The method includes forming a trench through the dielectric layer, and the trench includes a top portion and a bottom portion, and the trench is directly above the pixel region. The method includes forming a protection layer in the bottom portion of the trench and enlarging a top width of the top portion of the trench, and the trench has a wide top portion and a narrow bottom portion. The wide top portion has top sidewall surfaces, the narrow bottom portion has bottom sidewall surfaces, and the top sidewall surfaces taper gradually toward the bottom sidewall surfaces. The method includes filling a transparent dielectric layer in the trench to form a light pipe.

公开(公告)号：US20180331146A1

公开(公告)日：2018-11-15

申请号：US16040567

申请日：2018-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chun Hsu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Jeng-Shyan Lin ,  Shyh-Fann Ting

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L24/05 ,  H01L27/14603 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14685 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05566 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05686

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of interconnect layers within a dielectric structure over an upper surface of a substrate. A passivation structure is formed over the dielectric structure. The passivation structure has sidewalls and a horizontally extending surface defining has a recess within an upper surface of the passivation structure. A bond pad is formed having a lower surface overlying the horizontally extending surface and one or more protrusions extending outward from the lower surface. The one or more protrusions extend through one or more openings within the horizontally extending surface to contact a first one of the plurality of interconnect layers. An upper passivation layer is deposited on sidewalls and an upper surface of the bond pad and on sidewalls and the upper surface of the passivation structure.

公开(公告)号：US20170186796A1

公开(公告)日：2017-06-29

申请号：US14980225

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Jeng-Shyan Lin ,  Hsun-Ying Huang ,  Tzu-Hsuan Hsu

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14621 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/1469

Abstract: A frontside illuminated (FSI) image sensor with a reflector is provided. A photodetector is buried in a sensor substrate. A support substrate is arranged under and bonded to the sensor substrate. The reflector is arranged under the photodetector, between the sensor and support substrates, and is configured to reflect incident radiation towards the photodetector. A method for manufacturing the FSI image sensor and the reflector is also provided.