公开(公告)号：US11783873B2

公开(公告)日：2023-10-10

申请号：US17737734

申请日：2022-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih ,  Yi-Chun Shih ,  Chia-Fu Lee

IPC: G11C7/06 ,  G11C11/14 ,  G11C7/08 ,  G11C13/00 ,  H01L27/10

CPC classification number: G11C7/065 ,  G11C7/08 ,  G11C11/14 ,  G11C13/004 ,  H01L27/10

Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

公开(公告)号：US20210134352A1

公开(公告)日：2021-05-06

申请号：US16878594

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ku-Feng Lin

IPC: G11C11/408

Abstract: A word line driving device of a memory device is provided. The word line driving device of the memory device includes a word line, a word line driver, and a conducting line. The word line is disposed on a first metal layer. The word line is connected to a plurality of memory cells in a memory array. The word line driver is coupled to a first node of the word line. The conducting line is disposed on a second metal layer. The first node of the word line is coupled to a first node of the conducting line and a second node of the word line is coupled to a second node of the conducting line. The distance of the second metal layer with respect to a plurality of transistors in the memory device is greater than a distance of the first metal layer with respect to the plurality of transistors in the memory device.

公开(公告)号：US10998058B2

公开(公告)日：2021-05-04

申请号：US16736267

申请日：2020-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der Chih ,  Hung-Chang Yu ,  Ku-Feng Lin

IPC: G11C16/28 ,  G11C16/08 ,  G11C16/32 ,  G11C16/34 ,  G11C29/02 ,  G11C7/04

Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.

公开(公告)号：US10714535B2

公开(公告)日：2020-07-14

申请号：US16230798

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ku-Feng Lin ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Yu-Der Chih

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/18 ,  H01L27/088 ,  H01L23/532

Abstract: A method includes forming an insulator over a substrate. The insulator includes a first electrode, a second electrode, and a resistive element between the first electrode and the second electrode. The insulator is transformed into a resistor by applying a voltage to the insulator. The resistor is electrically connected to a transistor after transforming the insulator into the resistor.

公开(公告)号：US11386936B2

公开(公告)日：2022-07-12

申请号：US16925295

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/02 ,  G11C7/06

Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. The first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.

公开(公告)号：US11189336B2

公开(公告)日：2021-11-30

申请号：US16878594

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ku-Feng Lin

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4063 ,  G11C5/06 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00

Abstract: A word line driving device of a memory device is provided. The word line driving device of the memory device includes a word line, a word line driver, and a conducting line. The word line is disposed on a first metal layer. The word line is connected to a plurality of memory cells in a memory array. The word line driver is coupled to a first node of the word line. The conducting line is disposed on a second metal layer. The first node of the word line is coupled to a first node of the conducting line and a second node of the word line is coupled to a second node of the conducting line. The distance of the second metal layer with respect to a plurality of transistors in the memory device is greater than a distance of the first metal layer with respect to the plurality of transistors in the memory device.

公开(公告)号：US20210272606A1

公开(公告)日：2021-09-02

申请号：US16925295

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C7/06

Abstract: A memory device for sensing memory cell in a memory array includes at least one first memory cell, a first sensing amplifier, a first multiplexer circuit, a plurality of first reference cells, and a controller. The first sensing amplifier is coupled to the at least one first memory cell. An output terminal of the first multiplexer circuit is coupled to the reference terminal of the first sensing amplifier. Each of the first reference cells is coupled to each input node of the first multiplexer circuit. The controller is coupled to a control terminal of the first multiplexer circuit. the first sensing amplifier comprises an output terminal and a reference terminal. The controller controls the first multiplexer circuit to select one of the first reference cells as a selected reference cell to couple to the reference terminal of the first sensing amplifier when each read operation to the at least one first memory cell is performed.

公开(公告)号：US11024395B2

公开(公告)日：2021-06-01

申请号：US16023393

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der Chih ,  Hung-Chang Yu ,  Ku-Feng Lin

IPC: G11C16/28 ,  G11C16/08 ,  G11C16/32 ,  G11C16/34 ,  G11C29/02 ,  G11C7/04

Abstract: The present disclosure describes an adjustment circuit that can be used, for example, in a memory system with partitioned memory blocks. The adjustment circuit can include a controller circuit, a timer circuit, and a temperature adaptive reference (TAR) generator. The controller circuit can be configured to output a control signal that indicates a memory type (e.g., code memory or data memory) associated with a partitioned memory block. The timer circuit can be configured to output a timing signal for a read memory operation based on the control signal. And, the TAR generator can be configured to adjust a verify reference current for a verify memory operation based on temperature, where the verify reference current is set based on the control signal.

公开(公告)号：US10957366B2

公开(公告)日：2021-03-23

申请号：US16400222

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ku-Feng Lin ,  Yu-Der Chih ,  Yi-Chun Shih ,  Chia-Fu Lee

IPC: G11C7/06 ,  G11C13/00 ,  G11C7/08 ,  G11C11/14 ,  H01L27/10

Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

公开(公告)号：US09368552B2

公开(公告)日：2016-06-14

申请号：US14087782

申请日：2013-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ku-Feng Lin ,  Hung-Chang Yu ,  Kai-Chun Lin ,  Yue-Der Chih

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53257 ,  H01L25/18 ,  H01L27/088 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1641 ,  H01L45/1683

Abstract: A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.

Abstract translation: 制造电阻式存储器阵列的方法包括在第一衬底上形成多个绝缘体和导电结构，执行电阻器形成工艺以将绝缘体转换为多个电阻器，抛光导电结构以暴露多个接触点 分别电连接到电阻器，提供具有多个晶体管和多个互连焊盘的第二衬底，分别连接互连焊盘和接触点，以及从电阻器和导电结构去除第一衬底。