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27 条记录 (耗时 0.019 秒)

    Method and apparatus for MRAM sense reference trimming
    3.
    发明授权
    Method and apparatus for MRAM sense reference trimming 有权
    用于MRAM检测参考修整的方法和装置

    公开(公告)号：US09165629B2

    公开(公告)日：2015-10-20

    申请号：US13804773

    申请日：2013-03-14

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Yue-Der Chih ,  Kai-Chun Lin ,  Hung-Chang Yu

    IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C7/14 ,  G11C29/02

    CPC分类号： G11C11/1673 ,  G11C7/14 ,  G11C11/1675 ,  G11C29/021 ,  G11C29/028

    摘要： A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current.

    摘要翻译： 一种用于设置用于操作MRAM模块的参考电流的修整过程，该MRAM模块包括耦合到位线的操作MRAM单元，耦合到参考位线的多个参考MRAM单元以及耦合到位线和参考位线的读出放大器 在一些实施例中被公开。 该过程包括将位线参考电压施加到参考位线以提供通过多个参考MRAM单元的相应电流之和形成的参考单元电流。 检测参考单元电流。 确定检测到的参考单元电流是否与目标参考单元电流不同。 如果确定检测到的参考单元电流与目标参考单元电流不同，则位线参考电压被改变，或者感测放大器的感测比是变化的。

    Memory devices with improved refreshing operation
    6.
    发明授权
    Memory devices with improved refreshing operation 有权
    具有改善刷新操作的内存设备

    公开(公告)号：US09455006B2

    公开(公告)日：2016-09-27

    申请号：US14881492

    申请日：2015-10-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yue-Der Chih ,  Cheng-Hsiung Kuo ,  Gu-Huan Li ,  Chien-Yin Liu

    IPC分类号： G11C7/00 ,  G11C7/20 ,  G11C11/406 ,  G11C11/16 ,  G11C13/00 ,  G11C5/02

    CPC分类号： G11C7/20 ,  G11C5/02 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/406 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

    摘要： A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed

    摘要翻译： 公开了一种用于具有刷新操作的存储器单元编程和擦除的方法和系统。 该系统包括选择模块，处理模块和刷新模块。 在该方法中，首先，选择来自存储装置中的多个存储单元的目标存储单元。 此后，通过对目标存储单元施加选择电压和属于矩阵行的位置相关的存储单元来对属于矩阵行的目标存储单元进行编程或擦除。 然后，执行刷新位置相关单元的刷新操作

    Resistive memory array
    7.
    发明授权
    Resistive memory array 有权
    电阻式存储器阵列

    公开(公告)号：US09330746B2

    公开(公告)日：2016-05-03

    申请号：US14219350

    申请日：2014-03-19

    申请人： Taiwan Semiconductor Manufacturing CO., LTD.

    发明人： Kai-Chun Lin ,  Hung-Chang Yu ,  Ku-Feng Lin ,  Yue-Der Chih

    IPC分类号： G11C13/00 ,  G11C11/16

    CPC分类号： G11C11/1655 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1697 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/79 ,  G11C2213/82

    摘要： A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line.

    摘要翻译： 公开了一种包括电流源模块，电流吸收模块和存储体的电路。 电流源模块，电流模块和存储器组中的每一个都连接到第一位/源极线和第二位/源极线。 存储体由当前的源模块和当前的模块组成。 当电流源模块和电流接收模块从第一位/源线接收到触发脉冲和具有第一状态的选择信号时，电流源模块被激活以产生到第一位/源线的工作电流， 通过存储体的传导存储单元并且激活电流吸收模块以从第二位/源极线中漏去工作电流。

    Operating resistive memory cell
    8.
    发明授权
    Operating resistive memory cell 有权
    工作电阻式存储单元

    公开(公告)号：US09196360B2

    公开(公告)日：2015-11-24

    申请号：US14161193

    申请日：2014-01-22

    申请人： Taiwan Semiconductor Manufacturing CO., LTD.

    发明人： Chung-Cheng Chou ,  Yue-Der Chih

    IPC分类号： G11C13/00 ,  H03K17/56 ,  G11C11/56

    CPC分类号： G11C13/0064 ,  G11C11/56 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2213/79 ,  H03K17/56

    摘要： A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an injection current injected to the current comparator through the sensing node, wherein when a resistive state of the resistive memory cell switches such that the current comparator determines that an amount of the injection current increases to exceed or decreases to reach threshold value, the current comparator turns off the current source.

    摘要翻译： 公开了一种包括电流源和电流比较器的电路。 电流源连接到电阻存储器单元以产生驱动电流。 电流比较器具有连接到电流源和电阻存储器单元的感测节点，以感测通过感测节点注入到电流比较器的注入电流，其中当电阻性存储器单元的电阻状态切换使得电流比较器确定 注入电流的量增加到超过或者减小到达阈值时，电流比较器关闭电流源。