公开(公告)号：US20200075776A1

公开(公告)日：2020-03-05

申请号：US16678808

申请日：2019-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, an N-type bottom vertical gate-all-around (VGAA) transistor, a P-type bottom VGAA transistor, and a top VGAA transistor. The N-type bottom vertical gate-all-around (VGAA) transistor is over the semiconductor substrate and comprising a first nanowire made of InAs. The P-type bottom VGAA transistor is over the semiconductor substrate and comprising a second nanowire made of Ge. The top VGAA transistor is over the N-type bottom VGAA transistor, in which the top VGAA transistor includes a third nanowire in contact with the N-type bottom VGAA transistor, a fourth nanowire on and in contact with the third nanowire, and a bit line wrapping the fourth nanowire.

公开(公告)号：US20200027794A1

公开(公告)日：2020-01-23

申请号：US16585313

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a bottom portion, an intermediate portion disposed over the bottom portion and an upper portion disposed over the intermediate portion is formed. The intermediate portion is removed at a source/drain region of the fin structure, thereby forming a space between the bottom portion and the upper portion. An insulating layer is formed in the space. A source/drain contact layer is formed over the upper portion. The source/drain contact layer is separated by the insulating layer from the bottom portion of the fin structure.

公开(公告)号：US20190245037A1

公开(公告)日：2019-08-08

申请号：US16383528

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS ,  Matthias PASSLACK ,  Martin Christopher HOLLAND

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/20 ,  H01L29/775 ,  H01L21/306

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/7854

Abstract: A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.

公开(公告)号：US20190165182A1

公开(公告)日：2019-05-30

申请号：US15979854

申请日：2018-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device includes forming a nanowire foundation layer on a semiconductor substrate. A first nanowire is formed on the nanowire foundation layer. A gate structure is formed over the nanowire foundation layer and wrapping the first nanowire. A second nanowire is formed on and in contact with the first nanowire in a bottom-up manner. A source/drain region is formed on the gate structure and wrapping the second nanowire.

公开(公告)号：US20180323259A1

公开(公告)日：2018-11-08

申请号：US15588804

申请日：2017-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Martin Christopher HOLLAND ,  Mark VAN DAL ,  Georgios VELLIANITIS ,  Blandine DURIEZ ,  Gerben DOORNBOS

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/04

CPC classification number: H01L29/0847 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853

Abstract: A semiconductor device includes a plurality of fins. Each of the fins has a multi-layer stack comprising a first nanowire and a second nanowire. A first portion of the first nanowire and second nanowire are doped to form source and drain regions. An epitaxial layer wraps around the first portion of first nanowire and second nanowire over the source and drain region. A gate is disposed over a second portion of the first nanowire and second nanowire. The epitaxial layer is interposed in between the first nanowire and the second nanowire over the source and drain region. The epitaxial layer has a zig-zag contour.

公开(公告)号：US20180315833A1

公开(公告)日：2018-11-01

申请号：US15627568

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Blandine DURIEZ ,  Martin Christopher HOLLAND ,  Georgios VELLIANITIS ,  Mark VAN DAL

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate, a gate structure, a plurality of nanowires, a sacrificial material, and an epitaxy structure. The gate structure is disposed on and in contact with the substrate. The nanowires extend through the gate structure. The sacrificial material is separated from the gate structure. The epitaxy structure is in contact with the nanowires, is separated from the substrate, and surrounds the sacrificial material.

公开(公告)号：US20180166533A1

公开(公告)日：2018-06-14

申请号：US15669064

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ ,  Mark VAN DAL

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/465 ,  H01L29/24 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02639 ,  H01L21/465 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/66439 ,  H01L29/66969 ,  H01L29/785

Abstract: The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

公开(公告)号：US20200075777A1

公开(公告)日：2020-03-05

申请号：US16678820

申请日：2019-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A method includes forming a semiconductor fin over a substrate. A nanowire foundation layer is formed on the semiconductor fin. A nanowire template is formed over the nanowire foundation layer, in which the nanowire template has a through hole exposing a portion of the nanowire foundation layer. A first nanowire is grown from the exposed portion of the nanowire foundation layer, such that the nanowire protrudes out of the through hole. A gate structure is formed over the nanowire foundation layer and wrapping around the first nanowire.

公开(公告)号：US20200058750A1

公开(公告)日：2020-02-20

申请号：US16660455

申请日：2019-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Matthias PASSLACK ,  Martin Christopher HOLLAND

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/40 ,  H01L29/786 ,  H01L29/06 ,  H01L21/764 ,  H01L29/78 ,  H01L21/02 ,  B82Y10/00 ,  H01L21/762 ,  H01L29/20

Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby forming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.

公开(公告)号：US20190088649A1

公开(公告)日：2019-03-21

申请号：US15707682

申请日：2017-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gerben DOORNBOS ,  Mark VAN DAL

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from a first isolation insulating layer is formed. A second isolation insulating layer made of different material than the first isolation insulating layer is formed so that a first upper portion of the fin structure is exposed. A dummy gate structure is formed over the exposed first upper portion of the first fin structure. The second isolation insulating layer is etched by using the dummy gate structure as an etching mask. The dummy gate structure is removed so that a gate space is formed. The second isolation insulating layer is etched in the gate space so that a second upper portion of the fin structure is exposed from the first isolation insulating layer. A gate dielectric layer and a gate electrode layer are formed over the exposed second portion of the fin structure.