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公开(公告)号：US20220246766A1
公开(公告)日：2022-08-04
申请号：US17315687
申请日：2021-05-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mauricio Manfrini , Chih-Yu Chang , Sai-Hooi Yeong
IPC: H01L29/78 , H01L27/1159 , H01L21/02 , H01L21/443 , H01L29/66 , H01L29/24 , H01L29/45 , H01L29/786
Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. In some embodiments, the FeFET device includes a ferroelectric layer having a first side and a second side opposite to the first side and a gate electrode disposed along the first side of the ferroelectric layer. The FeFET device further includes an OS channel layer disposed along the second side of the ferroelectric layer opposite to the first side and a pair of source/drain regions disposed on opposite sides of the OS channel layer. The FeFET device further includes a 2D contacting layer disposed along the OS channel layer. The OS channel layer has a first doping type, and the 2D contacting layer has a second doping type different than the first doping type.
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公开(公告)号：US20210375990A1
公开(公告)日：2021-12-02
申请号：US17109427
申请日：2020-12-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Bo-Feng Young , Sheng-Chen Wang , Sai-Hooi Yeong , Yu-Ming Lin , Mauricio Manfrini , Han-Jong Chia
IPC: H01L27/24 , H01L27/22 , H01L29/24 , H01L29/786 , H01L29/66
Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.
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公开(公告)号：US20210375934A1
公开(公告)日：2021-12-02
申请号：US17130609
申请日：2020-12-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin , Mauricio Manfrini , Georgios Vellianitis
IPC: H01L27/11597 , H01L27/11587 , H01L27/1159
Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.
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公开(公告)号：US11107989B2
公开(公告)日：2021-08-31
申请号：US16531284
申请日：2019-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mauricio Manfrini , Marcus Johannes Henricus van Dal
Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a first ferromagnetic layer and a second ferromagnetic layer. A bottom electrode via overlies a substrate. A bottom electrode overlies the bottom electrode via. A data storage layer overlies the bottom electrode. The first ferromagnetic layer overlies the data storage layer and has a first magnetization pointing in a first direction. The second ferromagnetic layer overlies the bottom electrode via and has a second magnetization pointing in a second direction orthogonal to the first direct.
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公开(公告)号：US11107859B2
公开(公告)日：2021-08-31
申请号：US16531482
申请日：2019-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Katherine H. Chiang , Chung-Te Lin , Mauricio Manfrini
Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has a magnetic tunnel junction (MTJ) device disposed within a dielectric structure over a substrate. The MTJ device has a MTJ disposed between a first electrode and a second electrode. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector is configured to allow current to flow through the MTJ device along a first direction. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The second unipolar selector is configured to allow current to flow through the MTJ device along a second direction opposite the first direction.
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Patent Agency Ranking
公开(公告)号：US20210043837A1
公开(公告)日：2021-02-11
申请号：US16531284
申请日：2019-08-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mauricio Manfrini , Marcus Johannes Henricus van Dal
Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a first ferromagnetic layer and a second ferromagnetic layer. A bottom electrode via overlies a substrate. A bottom electrode overlies the bottom electrode via. A data storage layer overlies the bottom electrode. The first ferromagnetic layer overlies the data storage layer and has a first magnetization pointing in a first direction. The second ferromagnetic layer overlies the bottom electrode via and has a second magnetization pointing in a second direction orthogonal to the first direct
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公开(公告)号：US11737284B2
公开(公告)日：2023-08-22
申请号：US17562680
申请日：2021-12-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mauricio Manfrini , Hon-Sum Philip Wong
Abstract: A magnetoresistive random access memory (MRAM) cell includes a bottom electrode, a magnetic tunnel junction structure, a bipolar tunnel junction selector; and a top electrode. The tunnel junction selector includes a MgO tunnel barrier layer and provides a bipolar function for putting the MTJ structure in parallel or anti-parallel mode.
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公开(公告)号：US11586885B2
公开(公告)日：2023-02-21
申请号：US16371382
申请日：2019-04-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Marcus Johannes Henricus van Dal , Gerben Doornbos , Mauricio Manfrini
Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first memory element and a second memory element. The memory device includes a substrate and a bottom electrode disposed over the substrate. The first memory element is disposed between the bottom electrode and a top electrode, such that the first memory element has a first area. A second memory element is disposed between the bottom electrode and the top electrode. The second memory element is laterally separated from the first memory element by a non-zero distance. The second memory element has a second area different than the first area.
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公开(公告)号：US11527552B2
公开(公告)日：2022-12-13
申请号：US17130609
申请日：2020-12-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin , Mauricio Manfrini , Georgios Vellianitis
IPC: H01L27/11597 , H01L27/1159 , H01L27/11587 , H01L27/11585 , H01L29/66 , H01L29/51
Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.
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公开(公告)号：US20220123050A1
公开(公告)日：2022-04-21
申请号：US17562680
申请日：2021-12-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mauricio Manfrini , Hon-Sum Philip Wong
Abstract: A magnetoresistive random access memory (MRAM) cell includes a bottom electrode, a magnetic tunnel junction structure, a bipolar tunnel junction selector; and a top electrode. The tunnel junction selector includes a MgO tunnel barrier layer and provides a bipolar function for putting the MTJ structure in parallel or anti-parallel mode.
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