公开(公告)号：US20220359355A1

公开(公告)日：2022-11-10

申请号：US17870099

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US11495472B2

公开(公告)日：2022-11-08

申请号：US17065265

申请日：2020-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/498 ,  H01L21/56

Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

公开(公告)号：US11302600B2

公开(公告)日：2022-04-12

申请号：US16718211

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Chien-Yuan Huang ,  Chen-Hsiang Lao

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/42

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

公开(公告)号：US11728254B2

公开(公告)日：2023-08-15

申请号：US16881211

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US20220367208A1

公开(公告)日：2022-11-17

申请号：US17873640

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/498

Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

公开(公告)号：US20210327723A1

公开(公告)日：2021-10-21

申请号：US17065265

申请日：2020-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

公开(公告)号：US20210305145A1

公开(公告)日：2021-09-30

申请号：US16830284

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Huang ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Shang-Yun Hou

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

公开(公告)号：US20200312770A1

公开(公告)日：2020-10-01

申请号：US16561045

申请日：2019-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

公开(公告)号：US09824902B1

公开(公告)日：2017-11-21

申请号：US15207512

申请日：2016-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Chien-Hsun Lee ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Jung-Wei Cheng ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Ding Wang

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/28

CPC classification number: H01L21/568 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68386 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19102

Abstract: An integrated fan-out package including a chip module, a second integrated circuit, a second insulating encapsulation, and a redistribution circuit structure is provided. The chip module includes a first insulating encapsulation and a first integrated circuit embedded in the first insulating encapsulation, and the first integrated circuit includes a first surface and first conductive terminals on the first surface. The second integrated circuit includes a second surface and second conductive terminals on the second surface. The chip module and the second integrated circuit are embedded in the second insulating encapsulation. The first and second conductive terminals are accessibly exposed from the first and second insulating encapsulation. The redistribution circuit structure covers the first surface, the second surfaces, the first insulating encapsulation, and the second insulating encapsulation. The redistribution circuit structure is electrically connected to the first and second conductive terminals. Methods of fabricating the integrated fan-out package are also provided.