公开(公告)号：US10304848B2

公开(公告)日：2019-05-28

申请号：US15694611

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/11568

Abstract: An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

公开(公告)号：US20190057972A1

公开(公告)日：2019-02-21

申请号：US16167879

申请日：2018-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L29/423 ,  H01L27/11548 ,  H01L27/11534 ,  H01L21/28 ,  H01L27/11526 ,  H01L21/762 ,  H01L23/528

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US10134748B2

公开(公告)日：2018-11-20

申请号：US15694098

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L21/762 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/423 ,  H01L23/528

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US09716097B2

公开(公告)日：2017-07-25

申请号：US14596340

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yung-Chang Chang

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11534

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

公开(公告)号：US09691883B2

公开(公告)日：2017-06-27

申请号：US14308872

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7883

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

公开(公告)号：US11424255B2

公开(公告)日：2022-08-23

申请号：US16787952

申请日：2020-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Chyi Liu ,  Chih-Ren Hsieh ,  Sheng-Chieh Chen

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/762 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/788

Abstract: A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.

公开(公告)号：US11217596B2

公开(公告)日：2022-01-04

申请号：US16359027

申请日：2019-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/11517 ,  H01L27/11563

Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

公开(公告)号：US10734394B2

公开(公告)日：2020-08-04

申请号：US16732402

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L21/28 ,  H01L27/11534 ,  H01L21/762 ,  H01L29/423 ,  H01L27/11548 ,  H01L23/528

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US20200144276A1

公开(公告)日：2020-05-07

申请号：US16732402

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L21/762 ,  H01L27/11526 ,  H01L29/423

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US20170345835A1

公开(公告)日：2017-11-30

申请号：US15216872

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen

IPC: H01L27/11526 ,  H01L27/11521 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328

Abstract: The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.