公开(公告)号：US20230253301A1

公开(公告)日：2023-08-10

申请号：US18302112

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L23/49822 ,  H01L21/561 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L21/486 ,  H01L24/96 ,  H01L21/568 ,  H01L25/0657 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49894 ,  H01L25/50 ,  H01L24/81 ,  H01L24/19 ,  H01L23/3128 ,  H01L21/6835 ,  H01L21/56 ,  H01L2224/02331 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2924/181 ,  H01L2221/68372 ,  H01L2224/18 ,  H01L2924/18161 ,  H01L2221/68359

Abstract: A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.

公开(公告)号：US11296065B2

公开(公告)日：2022-04-05

申请号：US16901682

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L23/02 ,  H01L25/18 ,  H01L27/01 ,  H01L23/31 ,  H01L25/065 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US11114311B2

公开(公告)日：2021-09-07

申请号：US16242311

申请日：2019-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Shih-Ting Hung ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive structure over a substrate. The substrate includes a dielectric layer and a wiring layer in the dielectric layer, and the conductive structure is electrically connected to the wiring layer. The method includes forming a first molding layer over the substrate and surrounding the conductive structure. The method includes forming a redistribution structure over the first molding layer and the conductive structure. The method includes bonding a chip structure to the redistribution structure.

公开(公告)号：US12170274B2

公开(公告)日：2024-12-17

申请号：US17701083

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L27/01 ,  H01L49/02

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US12131984B2

公开(公告)日：2024-10-29

申请号：US18302112

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Techi Wong

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/18 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.

公开(公告)号：US11380666B2

公开(公告)日：2022-07-05

申请号：US17068026

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Meng-Wei Chou ,  Meng-Liang Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/18 ,  H01L23/00

Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

公开(公告)号：US11239173B2

公开(公告)日：2022-02-01

申请号：US16446796

申请日：2019-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Techi Wong ,  Shin-Puu Jeng

IPC: H01L21/98 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

Abstract: A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.

公开(公告)号：US20210351118A1

公开(公告)日：2021-11-11

申请号：US17383953

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Techi Wong ,  Meng-Wei Chou ,  Meng-Liang Lin ,  Po-Yao Chuang ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

公开(公告)号：US11094625B2

公开(公告)日：2021-08-17

申请号：US16406600

申请日：2019-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen Wu ,  Techi Wong ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Shih-Ting Hung ,  Shin-Puu Jeng

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.

公开(公告)号：US10515827B2

公开(公告)日：2019-12-24

申请号：US15874541

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/498 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

Abstract: A method for forming a chip package is provided. The method includes disposing a chip over a redistribution structure. The redistribution structure includes a first insulating layer and a first wiring layer, and the first wiring layer is in the first insulating layer and electrically connected to the chip. The method includes bonding an interposer substrate to the redistribution structure through a conductive structure. The chip is between the interposer substrate and the redistribution structure. The interposer substrate has a recess adjacent to the redistribution structure. A first portion of the chip is in the recess. The interposer substrate includes a substrate and a conductive via structure, and the conductive via structure passes through the substrate and is electrically connected to the first wiring layer through the conductive structure.