公开(公告)号：US20240153559A1

公开(公告)日：2024-05-09

申请号：US18417729

申请日：2024-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Der CHIH ,  Chung-Cheng CHOU ,  Wen-Ting CHU

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  H10B63/30 ,  H10B63/80 ,  H10B63/84 ,  H10N70/253 ,  H10N70/841 ,  G11C13/0007 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2213/79 ,  H10N70/20 ,  H10N70/826 ,  H10N70/8833

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

公开(公告)号：US20190164602A1

公开(公告)日：2019-05-30

申请号：US15870620

申请日：2018-01-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi TU ,  Chu-Jie HUANG ,  Sheng-Hung SHIH ,  Nai-Chao SU ,  Wen-Ting CHU

IPC: G11C13/00 ,  H01L21/02

Abstract: A memory device includes a bottom electrode, a resistance switching layer and a top electrode. The bottom electrode is over a metallization layer embedded in an inter-metal dielectric layer. The bottom electrode has a top surface and a sidewall that extends at an obtuse angle relative to the top surface. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.

公开(公告)号：US20150109850A1

公开(公告)日：2015-04-23

申请号：US14061539

申请日：2013-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yang CHANG ,  Chia-Fu LEE ,  Wen-Ting CHU ,  Yue-Der CHIH

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0026 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/16

Abstract: A device is disclosed that includes an I/O memory block. The I/O memory block includes memory cells, bit lines and a source line. The number of the formed bit lines is at least 4. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.

Abstract translation: 公开了一种包括I / O存储器块的装置。 I / O存储器块包括存储单元，位线和源极线。 所形成的位线的数量至少为4.位线和源极线电连接到存储器单元。 在I / O存储器块中，源线和位线被配置为向存储器单元提供逻辑数据。

公开(公告)号：US20150092471A1

公开(公告)日：2015-04-02

申请号：US14041916

申请日：2013-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Chun YOU ,  Kuo-Chi TU ,  Chih-Yang CHANG ,  Hsia-Wei CHEN ,  Yu-Wen LIAO ,  Chin-Chieh YANG ,  Sheng-Hung SHIH ,  Wen-Ting CHU

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0002 ,  G11C13/0059 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79

Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.

Abstract translation: 公开了一种包括以下概述的操作的方法。 在复位操作期间，第一电压被施加到每行存储单元的存取晶体管的栅极，其中存取晶体管的第一源极/漏极电连接到电阻随机存取存储器（RRAM）的第一电极 ）设备在同一个存储单元中。 当第一电压被施加到存取晶体管的栅极时，抑制电压被施加到RRAM器件的第二电极或多个未选择存储器单元中的每一个的存取晶体管的第二源极/漏极。

公开(公告)号：US20230380190A1

公开(公告)日：2023-11-23

申请号：US18361483

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Wen-Ting CHU ,  Yong-Shiuan TSAIR ,  Yu-Wen LIAO ,  Chih-Yang CHANG ,  Chin-Chieh YANG

IPC: H10B63/00 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10B51/30 ,  H10B51/40 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

公开(公告)号：US20230329128A1

公开(公告)日：2023-10-12

申请号：US18333145

申请日：2023-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsia-Wei CHEN ,  Chih-Hung PAN ,  Chih-Hsiang CHANG ,  Yu-Wen LIAO ,  Wen-Ting CHU

IPC: H10N70/00

CPC classification number: H10N70/8416 ,  H10N70/023 ,  H10B63/30

Abstract: A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.

公开(公告)号：US20180351099A1

公开(公告)日：2018-12-06

申请号：US15663671

申请日：2017-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jen-Sheng YANG ,  Wen-Ting CHU ,  Chih-Yang CHANG ,  Chin-Chieh YANG ,  Kuo-Chi TU ,  Sheng-Hung SHIH ,  Yu-Wen LIAO ,  Hsia-Wei CHEN ,  I-Ching CHEN

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1675 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76837 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/1616

Abstract: A semiconductor device includes an inter-metal dielectric layer, a memory cell, a transistor and a dielectric layer. The memory cell includes a metal-insulator-metal (MIM) structure over a top surface of the inter-metal dielectric layer. The transistor underlies the inter-metal dielectric layer. The dielectric layer extends over the transistor and along the top surface of the inter-metal dielectric layer. The dielectric layer is separated from the MIM structure.

公开(公告)号：US20160155499A1

公开(公告)日：2016-06-02

申请号：US15018726

申请日：2016-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yang CHANG ,  Chia-Fu LEE ,  Wen-Ting CHU ,  Yu-Der CHIH

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0026 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/16

Abstract: A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.

Abstract translation: 公开了一种包括存储器单元，位线和源极线的器件。 位线和源极线电连接到存储器单元。 在I / O存储器块中，源线和位线被配置为向存储器单元提供逻辑数据。

公开(公告)号：US20150131361A1

公开(公告)日：2015-05-14

申请号：US14079386

申请日：2013-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Ting CHU ,  Yue-Der CHIH

IPC: G11C29/02 ,  G11C13/00

CPC classification number: G11C29/76 ,  G11C13/0002 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/027 ,  G11C2029/4402

Abstract: A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.