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    PATTERNING A TRANSPARENT WAFER TO FORM AN ALIGNMENT MARK IN THE TRANSPARENT WAFER
    12.
    发明申请
    PATTERNING A TRANSPARENT WAFER TO FORM AN ALIGNMENT MARK IN THE TRANSPARENT WAFER 有权

    公开(公告)号：US20210375780A1

    公开(公告)日：2021-12-02

    申请号：US16884437

    申请日：2020-05-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Ping-Yin Liu

    IPC: H01L23/544 ,  H01L23/00

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

    Simultaneous bonding approach for high quality wafer stacking applications
    13.
    发明授权
    Simultaneous bonding approach for high quality wafer stacking applications 有权

    公开(公告)号：US11094575B2

    公开(公告)日：2021-08-17

    申请号：US16429145

    申请日：2019-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Chang-Chen Tsao

    IPC: H01L21/68 ,  H01L21/683 ,  H01L21/18 ,  H01L21/687

    Abstract: In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.

    Approach for ultra thin-film transfer and handling
    14.
    发明授权
    Approach for ultra thin-film transfer and handling 有权

    公开(公告)号：US10962878B2

    公开(公告)日：2021-03-30

    申请号：US16666679

    申请日：2019-10-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

    IPC: G03F7/20 ,  G03F1/64 ,  G03F1/62

    Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

    SIMULTANEOUS BONDING APPROACH FOR HIGH QUALITY WAFER STACKING APPLICATIONS
    15.
    发明申请
    SIMULTANEOUS BONDING APPROACH FOR HIGH QUALITY WAFER STACKING APPLICATIONS 审中-公开

    公开(公告)号：US20200381283A1

    公开(公告)日：2020-12-03

    申请号：US16429145

    申请日：2019-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Chang-Chen Tsao

    IPC: H01L21/683 ,  H01L21/68 ,  H01L21/687 ,  H01L21/18

    Abstract: In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.

    Conductive bond structure to increase membrane sensitivity in MEMS device
    18.
    发明授权
    Conductive bond structure to increase membrane sensitivity in MEMS device 有权

    公开(公告)号：US11292715B2

    公开(公告)日：2022-04-05

    申请号：US16601749

    申请日：2019-10-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Hua Lin ,  Chia-Ming Hung ,  Xin-Hua Huang ,  Yuan-Chih Hsieh

    IPC: B81C3/00 ,  B81B7/00 ,  B06B1/02 ,  B81C1/00

    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device including a conductive bonding structure disposed between a substrate and a MEMS substrate. An interconnect structure overlies the substrate. The MEMS substrate overlies the interconnect structure and includes a moveable membrane. A dielectric structure is disposed between the interconnect structure and the MEMS substrate. The conductive bonding structure is sandwiched between the interconnect structure and the MEMS substrate. The conductive bonding structure is spaced laterally between sidewalls of the dielectric structure. The conductive bonding structure, the MEMS substrate, and the interconnect structure at least partially define a cavity. The moveable membrane overlies the cavity and is spaced laterally between sidewalls of the conductive bonding structure.

    NOVEL APPROACH FOR ULTRA THIN-FILM TRANSFER AND HANDLING
    19.
    发明申请
    NOVEL APPROACH FOR ULTRA THIN-FILM TRANSFER AND HANDLING 审中-公开

    公开(公告)号：US20190094682A1

    公开(公告)日：2019-03-28

    申请号：US16013163

    申请日：2018-06-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

    IPC: G03F1/64 ,  G03F7/20

    CPC classification number: G03F1/64 ,  G03F1/62 ,  G03F7/7015

    Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

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