公开(公告)号：US11189515B2

公开(公告)日：2021-11-30

申请号：US16829248

申请日：2020-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hung Wang ,  Ping-Yin Liu ,  Yeong-Jyh Lin ,  Yeur-Luen Tu

IPC: H01L21/68 ,  G01B11/14 ,  H01L23/544 ,  H01L23/00

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

公开(公告)号：US10804234B2

公开(公告)日：2020-10-13

申请号：US16382503

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Bor-Ping Jang ,  Hsiao-Chung Liang

IPC: H01L25/10 ,  H01L23/14 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate and a first conductive pad arranged over the substrate. A boundary structure is on an upper surface of the substrate around the first conductive pad. The boundary structure has one or more sidewalls defining an opening with a round shape over the first conductive pad.

公开(公告)号：US20220320180A1

公开(公告)日：2022-10-06

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L27/22 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US20200227298A1

公开(公告)日：2020-07-16

申请号：US16829248

申请日：2020-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hung Wang ,  Ping-Yin Liu ,  Yeong-Jyh Lin ,  Yeur-Luen Tu

IPC: H01L21/68 ,  G01B11/14 ,  H01L23/544 ,  H01L23/00

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

公开(公告)号：US20190393067A1

公开(公告)日：2019-12-26

申请号：US16015507

申请日：2018-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hung Wang ,  Ping-Yin Liu ,  Yeong-Jyh Lin ,  Yeur-Luen Tu

IPC: H01L21/68 ,  G01B11/14 ,  H01L23/544 ,  H01L23/00

Abstract: Various embodiments of the present application are directed towards a method for workpiece-level alignment with low alignment error and high throughput. In some embodiments, the method comprises aligning a first alignment mark on a first workpiece to a field of view (FOV) of an imaging device based on feedback from the imaging device, and further aligning a second alignment mark on a second workpiece to the first alignment mark based on feedback from the imaging device. The second workpiece is outside the FOV during the aligning of the first alignment mark. The aligning of the second alignment mark is performed without moving the first alignment mark out of the FOV. Further, the imaging device views the second alignment mark, and further views the first alignment mark through the second workpiece, during the aligning of the second alignment mark. The imaging device may, for example, perform imaging with reflected infrared radiation.

公开(公告)号：US09834435B1

公开(公告)日：2017-12-05

申请号：US15363389

申请日：2016-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Xin-Hua Huang ,  Yeong-Jyh Lin ,  Jung-Huei Peng

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0058 ,  B81B2203/0315 ,  B81B2207/015 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/0172 ,  B81C2203/0735

Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a semiconductor substrate including a cavity and a movable feature in the cavity. The semiconductor device structure also includes a cap substrate bonded to the semiconductor substrate to seal the cavity. There is an interface between the cap substrate and the semiconductor substrate. The semiconductor device structure further includes a sealing feature embedded in the semiconductor substrate and surrounding the cavity. The sealing feature extends across the interface and penetrates through the cap substrate.

公开(公告)号：US09768142B2

公开(公告)日：2017-09-19

申请号：US13944334

申请日：2013-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yeong-Jyh Lin ,  Hsin-Hung Liao ,  Chien Ling Hwang ,  Bor-Ping Jang ,  Hsiao-Chung Liang ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/03 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45147 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.

公开(公告)号：US20170256513A1

公开(公告)日：2017-09-07

申请号：US15596392

申请日：2017-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ling Hwang ,  Yeong-Jyh Lin ,  Bor-Ping Jang ,  Hsiao-Chung Liang

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/147 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3841 ,  H01L2924/0665 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor device. In some embodiments, the semiconductor device has a first plurality of conductive pads arranged over a first substrate. A conductive solder material is arranged over and is electrically connected to the first plurality of conductive pads. A first boundary structure separates each conductive pad of the first plurality of conductive pads from an adjacent conductive pad of the first plurality of conductive pads. A die is arranged over the first substrate. The die has outermost sidewalls that are laterally separated from first and second ones of the first plurality of conductive pads by the first boundary structure.