公开(公告)号：US20250046667A1

公开(公告)日：2025-02-06

申请号：US18482217

申请日：2023-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Chieh Hsiao ,  Ke-Gang Wen ,  Chih-Pin Chiu ,  Hsin-Feng Chen ,  Yu-Bey Wu ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.

公开(公告)号：US20240355766A1

公开(公告)日：2024-10-24

申请号：US18448407

申请日：2023-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Pin Chiu ,  Yu-Bey Wu ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L23/485

CPC classification number: H01L24/06 ,  H01L23/485 ,  H01L24/03 ,  H01L2224/03005 ,  H01L2224/06102

Abstract: A first bond pad of a first device and a second bond pad of a second device are implanted with metal ions. The first and second semiconductor device are bonded together using a direct metal-to-metal bond and an overlay offset occurs between the bond pads such that a portion of the first bond pad and a portion of the second bond pad overlaps and contacts a dielectric material layer. During the bonding process, however, diffusion of the metal ions provides a barrier layer at the interface of the bond pads and the dielectric layers.

公开(公告)号：US11631745B2

公开(公告)日：2023-04-18

申请号：US17301431

申请日：2021-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US20180122738A1

公开(公告)日：2018-05-03

申请号：US15851671

申请日：2017-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheung-Hsuan Wei ,  Li Yu Lee ,  Tai-Yang Wu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  G06F17/50

CPC classification number: H01L23/528 ,  G06F17/5072 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

公开(公告)号：US11081445B2

公开(公告)日：2021-08-03

申请号：US16518430

申请日：2019-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheng-Hsuan Wei ,  Li-Yu Lee ,  Tai-Yang Wu

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/522 ,  G06F30/392

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

公开(公告)号：US10361156B2

公开(公告)日：2019-07-23

申请号：US15851671

申请日：2017-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheung-Hsuan Wei ,  Li-Yu Lee ,  Tai-Yang Wu

IPC: H01L21/76 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  G06F17/50 ,  H01L23/522

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

公开(公告)号：US09881870B2

公开(公告)日：2018-01-30

申请号：US15178115

申请日：2016-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheng-Hsuan Wei ,  Pei-Ru Lee ,  Tai-Yang Wu

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  G06F17/50 ,  H01L23/522

CPC classification number: H01L23/528 ,  G06F17/5072 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

公开(公告)号：US09653348B1

公开(公告)日：2017-05-16

申请号：US15157159

申请日：2016-05-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheng-Hsuan Wei ,  Pei-Ru Lee ,  Tai-Yang Wu

IPC: H01L21/26 ,  H01L21/768 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/033 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.