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公开(公告)号：US12219879B2
公开(公告)日：2025-02-04
申请号：US18521399
申请日：2023-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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12.发明授权公开(公告)号：US11217458B2
公开(公告)日：2022-01-04
申请号：US16895525
申请日：2020-06-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Hao Chen , Yu-Shu Chen , Yu-Cheng Liu
IPC: H01L21/31 , H01L21/311 , H01L21/027 , H01L21/3213 , H01L21/768 , H01L23/532
Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.
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公开(公告)号：US20210384418A1
公开(公告)日：2021-12-09
申请号：US17408648
申请日：2021-08-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Sin-Yi Yang , Chen-Jung Wang , Yu-Shu Chen , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Chih-Yuan Ting
Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
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14.发明授权公开(公告)号：US09425094B2
公开(公告)日：2016-08-23
申请号：US14583238
申请日：2014-12-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yungtzu Chen , Yu-Shu Chen , Yu-Cheng Liu
IPC: H01L21/768 , H01L21/311 , H01L21/02
CPC classification number: H01L21/76879 , H01L21/02126 , H01L21/02186 , H01L21/31116 , H01L21/31144 , H01L21/32136 , H01L21/76802 , H01L21/76807 , H01L21/76811 , H01L2221/1063
Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a hard mask layer over the dielectric layer. The method also includes performing a plasma etching process to etch the hard mask layer to form an opening, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The gas mixture has a volumetric concentration of the nitrogen-containing gas in a range from about 20% to about 30%. A volumetric concentration ratio of the carbon-containing gas to the halogen-containing gas in the gas mixture is equal to about 0.3. The method further includes etching the dielectric layer through the opening in the hard mask layer to form a feature opening in the dielectric layer. The method includes forming a conductive material in the feature opening.
Abstract translation: 提供一种形成半导体器件结构的方法。 该方法包括在半导体衬底上形成电介质层并在电介质层上形成硬掩模层。 该方法还包括执行等离子体蚀刻工艺以蚀刻硬掩模层以形成开口，并且在等离子体蚀刻工艺中使用的气体混合物包括含氮气体，含卤素气体和含碳气体。 气体混合物的含氮气体的体积浓度在约20％至约30％的范围内。 气体混合物中含碳气体与含卤素气体的体积浓度比等于约0.3。 该方法还包括通过硬掩模层中的开口蚀刻介电层，以形成电介质层中的特征开口。 该方法包括在特征开口中形成导电材料。
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公开(公告)号：US11800812B2
公开(公告)日：2023-10-24
申请号：US17688370
申请日：2022-03-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tai-Yen Peng , Chien-Chung Huang , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Han-Ting Lin , Chih-Yuan Ting , Jyu-Horng Shieh , Hui-Hsien Wei
Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.
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Patent Agency Ranking
公开(公告)号：US11665971B2
公开(公告)日：2023-05-30
申请号：US17408648
申请日：2021-08-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Sin-Yi Yang , Chen-Jung Wang , Yu-Shu Chen , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Chih-Yuan Ting
CPC classification number: H01L43/12 , H01L27/222 , H01L43/02
Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
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公开(公告)号：US20210098695A1
公开(公告)日：2021-04-01
申请号：US17120613
申请日：2020-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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18.发明授权Method for preventing extreme low-K (ELK) dielectric layer from being damaged during plasma process 有权用于防止极低K（ELK）电介质层在等离子体处理过程中损坏的方法公开(公告)号：US09355893B1
公开(公告)日：2016-05-31
申请号：US14600452
申请日：2015-01-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Hung-Hao Chen , Yu-Shu Chen , Yu-Cheng Liu
IPC: H01L21/768
CPC classification number: H01L21/76808 , H01L21/31138 , H01L21/76811 , H01L21/76813 , H01L21/76814
Abstract: A method for forming an interconnect structure is provided. The method includes providing a substrate. The method also includes forming a dielectric layer on the substrate, and the dielectric layer includes an extreme low-k (ELK) dielectric layer. The method includes forming a via hole in the dielectric layer and forming a photoresist in the via hole and on the dielectric layer. The method also includes removing the photoresist by a plasma process using a CxHyOz gas and forming a conductive structure in the via hole.
Abstract translation: 提供一种形成互连结构的方法。 该方法包括提供基板。 该方法还包括在衬底上形成电介质层，并且介电层包括极低k（ELK）电介质层。 该方法包括在电介质层中形成通孔，并在通孔和电介质层上形成光致抗蚀剂。 该方法还包括通过使用C x H y O z气体的等离子体工艺去除光致抗蚀剂并在通孔中形成导电结构。
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公开(公告)号：US20240099150A1
公开(公告)日：2024-03-21
申请号：US18521399
申请日：2023-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US20220367794A1
公开(公告)日：2022-11-17
申请号：US17869335
申请日：2022-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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