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    SEAL RING STRUCTURES AND METHODS OF FORMING SAME
    11.
    发明申请
    SEAL RING STRUCTURES AND METHODS OF FORMING SAME 审中-公开

    公开(公告)号：US20190109125A1

    公开(公告)日：2019-04-11

    申请号：US16201113

    申请日：2018-11-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

    IPC: H01L25/00 ,  H01L23/00 ,  H01L23/58 ,  H01L23/31 ,  H01L25/18 ,  H01L25/065

    Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

    HYBRID BOND PAD STRUCTURE
    13.
    发明申请
    HYBRID BOND PAD STRUCTURE 有权
    混合胶结结构

    公开(公告)号：US20160379960A1

    公开(公告)日：2016-12-29

    申请号：US14750003

    申请日：2015-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sin-Yao Huang ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Sheng-Chau Chen ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Yung-Lung Lin

    IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498

    CPC classification number: H01L25/0657 ,  H01L23/49838 ,  H01L23/52 ,  H01L25/50 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2225/06513 ,  H01L2225/06544

    Abstract: The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

    Abstract translation: 本发明涉及一种多维集成芯片，其具有在从背面接合焊盘侧向偏移的集成芯片裸片之间垂直延伸的再分配层。 多维集成芯片具有第一集成芯片裸片，其具有布置在第一半导体衬底的前侧上的第一级间介电层内的第一多个金属互连层。 所述多维集成芯片还具有第二集成芯片裸片，其具有设置在邻接所述第一ILD层的第二层间电介质层内的第二多个金属互连层。 接合焊盘设置在延伸穿过第二半导体衬底的凹部内。 重新分配层在从接合焊盘横向偏移的位置处在第一多个金属互连层和第二多个金属互连层之间垂直地延伸。

    3DIC structure and methods of forming
    14.
    发明授权
    3DIC structure and methods of forming 有权

    公开(公告)号：US11984431B2

    公开(公告)日：2024-05-14

    申请号：US18156848

    申请日：2023-01-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Ming Wu ,  Yung-Lung Lin ,  Zhi-Yang Wang ,  Sheng-Chau Chen ,  Cheng-Hsien Chou

    IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/06 ,  H01L25/50

    Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

    Seal ring structures and methods of forming same
    16.
    发明授权
    Seal ring structures and methods of forming same 有权

    公开(公告)号：US11342322B2

    公开(公告)日：2022-05-24

    申请号：US16933082

    申请日：2020-07-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

    IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

    Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

    Seal ring structures and methods of forming same
    18.
    发明授权
    Seal ring structures and methods of forming same 有权

    公开(公告)号：US10727218B2

    公开(公告)日：2020-07-28

    申请号：US16201113

    申请日：2018-11-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

    IPC: H01L25/00 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31

    Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

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