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    Low-k gate spacer and formation thereof
    11.
    发明授权
    Low-k gate spacer and formation thereof 有权

    公开(公告)号：US10854521B2

    公开(公告)日：2020-12-01

    申请号：US16674443

    申请日：2019-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

    Semiconductor device and method
    13.
    发明授权
    Semiconductor device and method 有权

    公开(公告)号：US12266541B2

    公开(公告)日：2025-04-01

    申请号：US17350206

    申请日：2021-06-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sung-En Lin ,  Chunyao Wang

    IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/311

    Abstract: In an embodiment, a method includes: forming a photoresist over a target layer; performing a plasma-enhanced deposition process, the plasma-enhanced deposition process etching sidewalls of the photoresist while depositing a spacer layer on the sidewalls of the photoresist; patterning the spacer layer to form spacers on the sidewalls of the photoresist; and etching the target layer using the spacers and the photoresist as a combined etching mask.

    Photolithography Methods and Resulting Structures
    15.
    发明公开
    Photolithography Methods and Resulting Structures 审中-公开

    公开(公告)号：US20240186142A1

    公开(公告)日：2024-06-06

    申请号：US18439340

    申请日：2024-02-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yi Chang ,  Chunyao Wang

    IPC: H01L21/027 ,  H01L21/308 ,  H01L21/477 ,  H01L29/66

    CPC classification number: H01L21/027 ,  H01L21/3086 ,  H01L21/477 ,  H01L29/66795

    Abstract: As deposited, hard mask thin films have internal stress components which are an artifact of the material, thickness, deposition process of the mask layer as well as of the underlying materials and topography. This internal stress can cause distortion and twisting of the mask layer when it is patterned, especially when sub-micron critical dimensions are being patterned. A stress-compensating process is employed to reduce the impact of this internal stress. Heat treatment can be employed to relax the stress, as an example. In another example, a second mask layer with an opposite internal stress component is employed to offset the internal stress component in the hard mask layer.

    Low-K Gate Spacer and Formation Thereof
    20.
    发明申请
    Low-K Gate Spacer and Formation Thereof 审中-公开

    公开(公告)号：US20200075419A1

    公开(公告)日：2020-03-05

    申请号：US16674443

    申请日：2019-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

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