公开(公告)号：US11204897B2

公开(公告)日：2021-12-21

申请号：US16669320

申请日：2019-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu An Tien ,  Changsheng Ying ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F16/174 ,  G06F16/16 ,  G06F30/392 ,  G06F30/34 ,  G06F30/36 ,  G06F30/39

Abstract: A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction. Multiple result files each in a compressed format are obtained from the distributed computing system and the result files are combined to obtain a single result file without decompressing and re-compressing the results from the distributed computing system.

公开(公告)号：US11093683B2

公开(公告)日：2021-08-17

申请号：US16559097

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G06F30/394

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

公开(公告)号：US11081354B2

公开(公告)日：2021-08-03

申请号：US16725731

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yuan Tseng ,  Wei-Liang Lin ,  Li-Te Lin ,  Ru-Gun Liu ,  Min Cao

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a mandrel over a substrate, the mandrel having a first sidewall and a second sidewall opposing the first sidewall; forming a first fin on the first sidewall and a second fin on the second sidewall; depositing a dielectric material covering the first fin, the second fin, and the mandrel; partially removing the dielectric material, thereby exposing the second fin; etching the second fin without etching the first fin and the mandrel; removing the dielectric material; and removing the mandrel.

公开(公告)号：US20210193504A1

公开(公告)日：2021-06-24

申请号：US17116443

申请日：2020-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC: H01L21/74 ,  H01L29/66 ,  H01L23/535

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US11043426B2

公开(公告)日：2021-06-22

申请号：US16578357

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.

公开(公告)号：US20210018849A1

公开(公告)日：2021-01-21

申请号：US16512767

申请日：2019-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Ming Chang ,  Chiu-Hsiang Chen ,  Ru-Gun Liu

IPC: G03F7/20

Abstract: A method for taking heat away from the photomask includes driving a working fluid to flow between a photomask and a fluid retaining structure and through a first slit of the fluid retaining structure, such that a boundary of the working fluid is confined between the photomask and the fluid retaining structure; and generating a light to irradiate the photomask through a light transmission region of the fluid retaining structure.

公开(公告)号：US10817635B2

公开(公告)日：2020-10-27

申请号：US16133110

申请日：2018-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien Hsieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Wen-Chun Huang ,  Wen-Li Cheng ,  Pai-Wei Wang

IPC: G06F30/39 ,  G03F1/36 ,  G03F1/70 ,  G06F119/18 ,  H01L27/02

Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.

公开(公告)号：US10790155B2

公开(公告)日：2020-09-29

申请号：US16240402

申请日：2019-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Chih-Ming Lai ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Ken-Hsien Hsieh ,  Chin-Hsiang Lin

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

公开(公告)号：US20200279743A1

公开(公告)日：2020-09-03

申请号：US16877755

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

公开(公告)号：US20200098631A1

公开(公告)日：2020-03-26

申请号：US16531232

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L21/768 ,  G06F17/50

Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.