公开(公告)号：US11450663B2

公开(公告)日：2022-09-20

申请号：US17104891

申请日：2020-11-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Cheng Chen ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Lo-Heng Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

公开(公告)号：US12074204B2

公开(公告)日：2024-08-27

申请号：US17384667

申请日：2021-07-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jung-Hung Chang ,  Lo Heng Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chien-Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L21/823475 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/78696

摘要： A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.

公开(公告)号：US11901364B2

公开(公告)日：2024-02-13

申请号：US17459101

申请日：2021-08-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Hung Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L27/12 ,  H01L21/822 ,  H01L21/8234

CPC分类号： H01L27/1207 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

公开(公告)号：US11710774B2

公开(公告)日：2023-07-25

申请号：US17238505

申请日：2021-04-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Hung Chang ,  Zhi-Chang Lin ,  Shih-Cheng Chen ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/308

CPC分类号： H01L29/41791 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/785 ,  H01L2029/7858

摘要： The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

公开(公告)号：US20220320309A1

公开(公告)日：2022-10-06

申请号：US17219410

申请日：2021-03-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Zhi-Chang Lin

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： A semiconductor device includes a substrate, a first source/drain feature and a second source/drain feature over the substrate, a first semiconductor layer and a second semiconductor layer between the first and the second source/drain features, and a gate between the first and the second source/drain features. A portion of the gate is further between the first and the second semiconductor layers. Moreover, the semiconductor device includes a first inner spacer and a second inner spacer. The first inner spacer is between the first and the second semiconductor layers and further between the portion of the gate and a portion of the first source/drain feature. Furthermore, the portion of the first source/drain feature is between the first semiconductor layer and the second semiconductor layer. The first inner spacer has a U-shaped profile. Additionally, the second inner spacer is between the first inner spacer and the portion of the first source/drain feature.

公开(公告)号：US09431517B2

公开(公告)日：2016-08-30

申请号：US14594001

申请日：2015-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/823885 ,  H01L23/544 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

摘要翻译： 通过初始形成彼此平坦的第一掺杂区域和第二掺杂区域来形成周围器件的垂直栅极。 沟道层形成在第一掺杂区域和第二掺杂区域之上，并且在沟道层上形成第三掺杂区域。 第四掺杂区域形成为与第三掺杂区域平面，并且第一掺杂区域，第二掺杂区域，第三掺杂区域，第四掺杂区域和沟道层被图案化以形成第一纳米线，第二掺杂区域 纳米线，然后用于形成围绕设备的垂直门。

公开(公告)号：US09406780B2

公开(公告)日：2016-08-02

申请号：US14594001

申请日：2015-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L21/20 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

公开(公告)号：US20160149019A1

公开(公告)日：2016-05-26

申请号：US14594001

申请日：2015-01-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hong-Lin Chen ,  Shih-Cheng Chen ,  Ming-Shan Shieh ,  Chin-Chi Wang ,  Wai-Yi Lien ,  Chih-Hao Wang

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L27/0924 ,  H01L21/823885 ,  H01L23/544 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L2029/7858 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer. A fourth doped region is formed to be planar with the third doped region, and the first doped region, the second doped region, the third doped region, the fourth doped region, and the channel layer are patterned to form a first nanowire and a second nanowire, which are then used to form the vertical gate all around devices.

公开(公告)号：US20230395655A1

公开(公告)日：2023-12-07

申请号：US17832681

申请日：2022-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Cheng Chen ,  Zhi-Chang Lin ,  Jung-Hung Chang ,  Chien-Ning Yao ,  Tsung-Han Chuang ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66

CPC分类号： H01L29/0649 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/31111 ,  H01L29/66553 ,  H01L29/66742

摘要： Provided are a semiconductor device and a method of forming the same. The semiconductor device includes at least two active strip regions, a hybrid fin structure, and a gate stack. The hybrid fin structure is disposed between the at least two active strip regions. The gate stack is across the at least two active strip regions and the hybrid fin structure. A portion of the hybrid fin structure exposed by the gate stack is free of a high dielectric constant material.

公开(公告)号：US11699760B2

公开(公告)日：2023-07-11

申请号：US17140532

申请日：2021-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Jung-Hung Chang ,  Chien Ning Yao ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/78 ,  H01L27/06

CPC分类号： H01L29/7855 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0688 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/7858

摘要： A semiconductor device according to the present disclosure includes a stack of first channel members, a stack of second channel members disposed directly over the stack of first channel members, a bottom source/drain feature in contact with the stack of the first channel members, a separation layer disposed over the bottom source/drain feature, a top source/drain feature in contact with the stack of second channel members and disposed over the separation layer, and a frontside contact that extends through the top source/drain feature and the separation layer to be electrically coupled to the bottom source/drain feature.