公开(公告)号：US07365412B2

公开(公告)日：2008-04-29

申请号：US11279434

申请日：2006-04-12

申请人： Timothy J. Dalton ,  Jeffrey P. Gambino ,  Anthony K. Stamper

发明人： Timothy J. Dalton ,  Jeffrey P. Gambino ,  Anthony K. Stamper

IPC分类号： H01L29/00

CPC分类号： H01G4/33 ,  H01G4/236 ,  H01L28/91 ,  Y10T29/435

摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.

摘要翻译： 电容器结构使用位于电介质层内的开口依次位于衬底上。 嵌入电介质层内的一对导体互连层终止于孔的一对相对的侧壁。 一对电容器板位于孔的一对相对的侧壁上，并接触一对导体互连层，但不填充孔。 电容器介质层位于一对电容器板之间并填充孔。 可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。 或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的侧壁是垂直的并且被向外倾斜的第二对相对的侧壁隔开时。

公开(公告)号：US20080003759A1

公开(公告)日：2008-01-03

申请号：US11427457

申请日：2006-06-29

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

公开(公告)号：US20120133022A1

公开(公告)日：2012-05-31

申请号：US13359634

申请日：2012-01-27

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/92 ,  H01L29/8605

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US08120143B2

公开(公告)日：2012-02-21

申请号：US12034728

申请日：2008-02-21

申请人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Sarah L. Lane ,  Anthony K. Stamper

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76831 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

摘要翻译： 本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。 本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

公开(公告)号：US07892940B2

公开(公告)日：2011-02-22

申请号：US11851123

申请日：2007-09-06

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。

公开(公告)号：US20080224259A1

公开(公告)日：2008-09-18

申请号：US12106374

申请日：2008-04-21

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

公开(公告)号：US07394145B2

公开(公告)日：2008-07-01

申请号：US11928798

申请日：2007-10-30

申请人： Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在所述电介质层中形成通过所述介电层与所述无源元件的互连以及与所述虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。

公开(公告)号：US08232190B2

公开(公告)日：2012-07-31

申请号：US11865079

申请日：2007-10-01

申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

IPC分类号： H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。

公开(公告)号：US20080254630A1

公开(公告)日：2008-10-16

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. EDELSTEIN ,  Matthew E. Colburn ,  Edward C. Cooney ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. EDELSTEIN ,  Matthew E. Colburn ,  Edward C. Cooney ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/311

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US07427550B2

公开(公告)日：2008-09-23

申请号：US11427457

申请日：2006-06-29

申请人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L21/76819 ,  H01L23/522 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

摘要翻译： 公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。 虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。 该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。 该方法消除了平面化的需要。