公开(公告)号：US20050085045A1

公开(公告)日：2005-04-21

申请号：US10687839

申请日：2003-10-20

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/331 ,  H01L21/762 ,  H01L29/786

CPC classification number: H01L29/78609 ,  H01L21/76281

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract translation: 绝缘体上硅（SOI）器件的制造方法包括在SOI衬底中限定有源区，用给定导电类型的杂质掺杂整个有源区，掩蔽有源区的主要部分，并掺杂 有源区的外围部分至少两次，其中杂质具有相同的导电类型，优选地每次使用不同的掺杂参数。 附加掺杂在有源区域的外围部分中产生通道阻挡，抵消在有源区域的外围部分中晶体管阈值电压降低的趋势，从而减轻或消除在晶体管工作中经常发现的不希望的阈值突峰 特征，例如，完全耗尽的SOI器件。

公开(公告)号：US06362474B1

公开(公告)日：2002-03-26

申请号：US09386369

申请日：1999-08-31

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01J37317

CPC classification number: G01N1/32 ,  G01N2033/0095 ,  H01J2237/26

Abstract: Described here is a method of forming a thin-film portion for allowing electrons produced from a transmission electron microscope to pass therethrough at a portion to be observed of a semiconductor and effecting a predetermined etching process on the thin-film portion thereby to create a semiconductor sample for the transmission electron microscope. Prior to the execution of the etching process, grooves for reducing a stress introduced into the thin-film portion by the etching process are defined in the thin-film portion.

Abstract translation: 这里描述的是形成用于使透射电子显微镜产生的电子在半导体观察部分通过的薄膜部分的方法，并对薄膜部分进行预定的蚀刻工艺，从而形成半导体 样品用于透射电子显微镜。 在执行蚀刻工艺之前，在薄膜部分中限定用于通过蚀刻工艺减小引入薄膜部分的应力的沟槽。

公开(公告)号：US09136386B2

公开(公告)日：2015-09-15

申请号：US13362093

申请日：2012-01-31

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78603 ,  H01L21/76254 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78621

Abstract: An SOI substrate includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film.

Abstract translation: SOI衬底包括半导体基底; 形成在半导体基底上的半导体层; 以及掩埋绝缘膜，其设置在半导体基底和半导体层之间，以将半导体层与半导体基底电隔离，其中埋入绝缘膜包含氮化物膜。

公开(公告)号：US20110101458A1

公开(公告)日：2011-05-05

申请号：US12929282

申请日：2011-01-12

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0266 ,  H01L29/78

Abstract: An SOI type semiconductor device having a silicon substrate and a buried oxide layer formed on the silicon substrate includes an internal circuit formed in a first region having at least one FD type transistor having a SOI structure, the internal circuit performing a function of the semiconductor device and a protection circuit formed in a second region having at least one PD type transistor having a SOI structure, the protection circuit protecting the internal circuit from electro static damage.

Abstract translation: 具有在硅衬底上形成的硅衬底和掩埋氧化层的SOI型半导体器件包括形成在具有SOI结构的至少一个FD型晶体管的第一区域中的内部电路，该内部电路执行半导体器件的功能 以及形成在具有至少一个具有SOI结构的PD型晶体管的第二区域中的保护电路，所述保护电路保护所述内部电路免受静电损坏。

公开(公告)号：US07300851B2

公开(公告)日：2007-11-27

申请号：US11331258

申请日：2006-01-13

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/331

CPC classification number: H01L29/78609 ,  H01L21/76281

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract translation: 绝缘体上硅（SOI）器件的制造工艺包括在501衬底中限定有源区，用给定导电类型的杂质掺杂整个有源区，掩蔽有源区的主要部分，并掺杂 有源区的外围部分至少两次，其中杂质具有相同的导电类型，优选地每次使用不同的掺杂参数。 附加的掺杂在有源区域的外围部分中产生通道停止，抵消在有源区域的外围部分中晶体管阈值电压降低的倾向，从而减轻或消除在晶体管中经常发现的不希望的次阈值突峰 例如，完全耗尽的SOI器件的工作特性。

公开(公告)号：US07112501B2

公开(公告)日：2006-09-26

申请号：US10687839

申请日：2003-10-20

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/331

CPC classification number: H01L29/78609 ,  H01L21/76281

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract translation: 绝缘体上硅（SOI）器件的制造方法包括在SOI衬底中限定有源区，用给定导电类型的杂质掺杂整个有源区，掩蔽有源区的主要部分，并掺杂 有源区的外围部分至少两次，其中杂质具有相同的导电类型，优选地每次使用不同的掺杂参数。 附加掺杂在有源区域的外围部分中产生通道阻挡，抵消在有源区域的外围部分中晶体管阈值电压降低的趋势，从而减轻或消除在晶体管工作中经常发现的不希望的阈值突峰 特征，例如，完全耗尽的SOI器件。

公开(公告)号：US5892225A

公开(公告)日：1999-04-06

申请号：US766613

申请日：1996-12-13

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: G01N1/28 ,  G01N1/32 ,  G01R31/307 ,  H01J37/295 ,  H01J37/26

CPC classification number: G01R31/307 ,  G01N1/32

Abstract: A plan-view sample of an integrated circuit is prepared for transmission electron microscopy by marking a faulty circuit element, lapping the upper surface of the sample to a mirror finish, lapping the lower surface to reduce the thickness of the entire sample, and further processing the lower surface by lapping or dimpling, combined with ion milling as necessary, to thin the sample in the vicinity of the fault. A sample prepared in this way affords a wide view, and can be tilted at large angles. A known thickness of a particular type of layer in the sample can be left by holding the sample at a predetermined angle while the sample is lapped.

Abstract translation: 通过标记故障电路元件，将样品的上表面研磨成镜面，制备集成电路的平面图样品用于透射电子显微镜，研磨下表面以减小整个样品的厚度，并进一步处理 通过研磨或凹坑的下表面，结合根据需要的离子铣削，使样品在故障附近变薄。 以这种方式制备的样品可以获得宽视角，并且可以以大的角度倾斜。 通过在样品被研磨的同时将样品保持在预定角度，可以留下样品中特定类型的层的已知厚度。

公开(公告)号：US20130043537A1

公开(公告)日：2013-02-21

申请号：US13583409

申请日：2011-03-09

Applicant: Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

Inventor： Yasuo Arai ,  Masao Okihara ,  Hiroki Kasai

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/14658 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1443 ,  H01L27/1461 ,  H01L27/14612 ,  H01L29/66477 ,  H01L29/78648 ,  H01L29/8611

Abstract: There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

公开(公告)号：US08362562B2

公开(公告)日：2013-01-29

申请号：US12659947

申请日：2010-03-25

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823878

Abstract: In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region.

Abstract translation: 在具有均匀晶体管特性的绝缘体上硅（SOI）结构的半导体器件中，N型晶体管的栅电极形成位置与P型半导体区域的端部之间的第一距离大于栅极之间的第二距离 P型晶体管的电极形成位置和N型半导体区域的边缘。

公开(公告)号：US08217361B2

公开(公告)日：2012-07-10

申请号：US12230976

申请日：2008-09-09

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: G01J1/42

CPC classification number: G01J1/429 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/103

Abstract: An ultraviolet sensor has an ultraviolet detection diode having a depletion region 18 formed in an Si layer 16 on an insulating layer 14, an interlayer insulating film 20 formed on the ultraviolet detection diode, and a wiring 24 formed on the interlayer insulating film 20. An incident angle θ (°) of an incident light entering into the depletion region 18 and a film thickness Tsi (nm) of the depletion region 18 satisfy the following formula (1), which is also shown in FIG. 14. TSi≦TSi/sin θ≦100  (Formula 1)

Abstract translation: 紫外线传感器具有紫外线检测二极管，其具有形成在绝缘层14上的Si层16中的耗尽区18，形成在紫外检测二极管上的层间绝缘膜20以及形成在层间绝缘膜20上的布线24。 入射角度和角度; 入射到耗尽区18的入射光的（°）和耗尽区18的膜厚Tsi（nm）满足下面的公式（1），其也在图1中示出。 TSi＆nlE; TSi / sin＆Thetas;＆nlE; 100（公式1）