公开(公告)号：US09529254B2

公开(公告)日：2016-12-27

申请号：US14504401

申请日：2014-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsien Tang ,  Yao-Jen Fan ,  Chin-Lung Lin

IPC: G03B27/32 ,  G03F1/00 ,  G06F17/50 ,  G03F1/70 ,  G03F7/20

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5081

Abstract: A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.

Abstract translation: 布局模式分解方法包括以下步骤。 接收到布局模式。 布局图案包括多个特征，并且在两个相邻特征之间分别限定边缘到边缘空间。 边缘至边缘空间的宽度和边缘至边缘空间的左侧上的特征的宽度的总和以及边缘至边缘空间的宽度和宽度之和 分别计算边缘到边缘空间右侧的特征。 分别对和值和预定值进行比较。 当总和中的任何一个小于预定值时，边缘到边缘空间的两侧上的两个特征被第一颜色和第二颜色着色。 包括第一颜色的特征被分配给第一图案，并且将包括第二颜色的特征分配给第二图案。

公开(公告)号：US20160358813A1

公开(公告)日：2016-12-08

申请号：US14733930

申请日：2015-06-08

Applicant: United Microelectronics Corp.

Inventor： Harn-Jiunn Wang ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0334 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76229

Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.

Abstract translation: 提供了一种形成沟槽的方法。 在基板上形成第一层，第二层和第三层。 形成具有多个第三沟槽的图案化第三层。 间隔件形成在第三沟槽的侧壁上，接着通过去除第三沟槽之间的图案化第三层的一部分。 通过使用间隔物和图案化的第三层作为掩模，形成具有多个第二沟槽的图案化的第二层。 接下来，完全去除图案化的第三层和间隔物，并且在图案化的第二层上形成阻挡层，填充到至少一个第二沟槽中，以将所述第二沟槽分成至少两个部分。 通过使用图案化的第二层和阻挡层作为掩模来对第一层进行构图，以形成具有第一沟槽的图案化的第一层。

公开(公告)号：US20150137369A1

公开(公告)日：2015-05-21

申请号：US14607051

申请日：2015-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Wen Fang ,  Chin-Lung Lin ,  Kuo-Chang Tien ,  Yi-Hsiu Lee ,  Chien-Hsiung Wang

IPC: H01L23/528 ,  G03F1/36 ,  H01L23/532 ,  G06F17/50 ,  H01L23/522

CPC classification number: H01L23/528 ,  G03F1/144 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077 ,  G06T2207/30148 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.

Abstract translation: 由计算机系统执行的用于修改线路图案的光学邻近校正的方法包括以下步骤。 首先，提供具有与平行线图案相对布置的平行线图案和互连图案的集成电路布局。 然后，使用计算机基于互连图案的位置来修改集成电路布局，以便分别在每个平行线图案的两侧上产生凸部和凹部。 在凸部和凹部之前和之后的线图案的部分是直线并且具有相同的临界尺寸。

公开(公告)号：US20210202492A1

公开(公告)日：2021-07-01

申请号：US17202359

申请日：2021-03-16

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.

公开(公告)号：US20190189620A1

公开(公告)日：2019-06-20

申请号：US16177348

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L27/10885 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

公开(公告)号：US09530731B2

公开(公告)日：2016-12-27

申请号：US14607051

申请日：2015-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Wen Fang ,  Chin-Lung Lin ,  Kuo-Chang Tien ,  Yi-Hsiu Lee ,  Chien-Hsiung Wang

IPC: G03F1/00 ,  G06F17/50 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  G03F1/144 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077 ,  G06T2207/30148 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.

Abstract translation: 由计算机系统执行的用于修改线路图案的光学邻近校正的方法包括以下步骤。 首先，提供具有与平行线图案相对布置的平行线图案和互连图案的集成电路布局。 然后，使用计算机基于互连图案的位置来修改集成电路布局，以便分别在每个平行线图案的两侧上产生凸部和凹部。 在凸部和凹部之前和之后的线图案的部分是直线并且具有相同的临界尺寸。

公开(公告)号：US20160314233A1

公开(公告)日：2016-10-27

申请号：US14692723

申请日：2015-04-21

Applicant: United Microelectronics Corp.

Inventor： Harn-Jiunn Wang ,  Kuei-Chun Hung ,  Chih-Hsien Tang ,  Chin-Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method of decomposing pattern layout for generating patterns on photomasks is disclosed. The method includes decomposing features of an integrated circuit layout into discrete patterns based on the relation between these features. The features include first features and second features. The first features are then classified into a first feature pattern and a second feature pattern, and the second features are classified into third, fourth, fifth and sixth feature patterns. The spacings of the second features in the fifth and sixth feature patterns are greater than a minimum exposure limits. Finally, the first feature pattern is outputted to a first photomask, the second feature pattern is outputted to a second photomask, the third and fifth feature patterns are outputted to a third photomask, and the fourth and sixth feature patterns are outputted to a fourth photomask.

Abstract translation: 公开了一种分解用于在光掩模上产生图案的图案布局的方法。 该方法包括基于这些特征之间的关系将集成电路布局的特征分解为离散模式。 功能包括第一个功能和第二个功能。 然后将第一特征分类为第一特征图案和第二特征图案，并且将第二特征分类为第三，第四，第五和第六特征图案。 第五和第六特征图案中的第二特征的间距大于最小暴露极限。 最后，将第一特征图案输出到第一光掩模，将第二特征图案输出到第二光掩模，将第三和第五特征图案输出到第三光掩模，并将第四和第六特征图案输出到第四光掩模 。

公开(公告)号：US20160306912A1

公开(公告)日：2016-10-20

申请号：US14690481

申请日：2015-04-20

Applicant: United Microelectronics Corp.

Inventor： Yen-Hung Chen ,  Chin-Lung Lin ,  Kuan-Wen Fang ,  Po-Ching Su ,  Hung-Wei Lin ,  Sheng-Lung Teng ,  Lun-Wen Yeh

IPC: G06F17/50 ,  H01L21/768 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  H01L21/76807

Abstract: An optical proximity correction (OPC) process is provided. The method comprising receiving a first pattern corresponding to a first structure of a semiconductor structure, and a second pattern corresponding to a second structure of said semiconductor structure. Next, a first OPC process is performed for the first pattern to obtain a revised first pattern, wherein the revised first pattern has a first shift regarding to the first pattern. A second OPC process is performed for the second pattern to obtain a revised second pattern, wherein the second OPC process comprises moving the second pattern according to the first shift.

Abstract translation: 提供光学邻近校正（OPC）过程。 该方法包括接收对应于半导体结构的第一结构的第一图案，以及对应于所述半导体结构的第二结构的第二图案。 接下来，对第一图案执行第一OPC处理以获得修改的第一图案，其中修改的第一图案具有关于第一图案的第一移位。 对第二图案执行第二OPC处理以获得修订的第二图案，其中第二OPC处理包括根据第一移位移动第二图案。

公开(公告)号：US10969687B2

公开(公告)日：2021-04-06

申请号：US16209871

申请日：2018-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Kai-Ming Liu ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: G03F7/20 ,  H01L21/3213 ,  H01L21/027

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.

公开(公告)号：US20190187562A1

公开(公告)日：2019-06-20

申请号：US16209871

申请日：2018-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Harn-Jiunn Wang ,  Kai-Ming Liu ,  Chin-Lung Lin ,  Yi-Hsiu Lee

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/3213

CPC classification number: G03F7/2022 ,  H01L21/027 ,  H01L21/3213

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.