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公开(公告)号：US20150072272A1
公开(公告)日：2015-03-12
申请号：US14023476
申请日：2013-09-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Ming-Jui Chen , Chia-Wei Huang , Hsin-Yu Chen , Kai-Lin Chuang
Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.
Abstract translation: 提供一种形成光掩模的方法。 提供与第一行相关的第一照片掩模图案，与第一通孔插头相关的原始第二照片掩模图案和与第二行相关的第三照片掩模图案。 执行第一光学邻近校正（OPC）处理。 执行第二OPC处理，包括沿着第一方向放大第二光掩模图案的宽度以形成修改的第二光刻胶图案。 执行轮廓模拟处理以确保修改的第二光掩模图案大于或等于原始第二掩模图案。 输出第一光掩模图案，修改的第二光掩模图案和第三光掩模图案。 本发明还提供一种OPC方法。
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公开(公告)号：US20140220482A1
公开(公告)日：2014-08-07
申请号：US14259173
申请日：2014-04-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hsin-Yu Chen , Chia-Wei Huang , Chun-Hsien Huang , Shih-Chun Tsai , Kai-Lin Chuang
IPC: G03F1/36
Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.
Abstract translation: 形成图案的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一布局。 提供包括第二目标图案和第二可打印虚拟图案的第二布局，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚设图案不能形成在晶片中。
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公开(公告)号：US08748066B2
公开(公告)日：2014-06-10
申请号：US13633876
申请日：2012-10-03
Applicant: United Microelectronics Corp.
Inventor： Hsin-Yu Chen , Chia-Wei Huang , Chun-Hsien Huang , Shih-Chun Tsai , Kai-Lin Chuang
IPC: G03F9/00
Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.
Abstract translation: 一种形成光掩模的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一光掩模。 提供了包括第二目标图案和第二可打印虚设图案的第二光掩模，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚拟图案不能被印刷在晶片 。
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公开(公告)号：US20140093814A1
公开(公告)日：2014-04-03
申请号：US13633876
申请日：2012-10-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hsin-Yu Chen , Chia-Wei Huang , Chun-Hsien Huang , Shih-Chun Tsai , Kai-Lin Chuang
IPC: G03F1/68
Abstract: A method for forming photomasks includes the following steps. A first photomask including a first target pattern and a first unprintable dummy pattern is provided. A second photomask including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlapping the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern can not be printed in a wafer.
Abstract translation: 一种形成光掩模的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一光掩模。 提供了包括第二目标图案和第二可打印虚设图案的第二光掩模，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚拟图案不能被印刷在晶片 。
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公开(公告)号：US20250040228A1
公开(公告)日：2025-01-30
申请号：US18916723
申请日：2024-10-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Chien-Hung Chen , Li-Ping Huang , Chun-Yen Tseng
IPC: H01L29/423 , G11C5/06 , G11C11/412 , H01L29/78 , H10B10/00
Abstract: The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.
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Patent Agency Ranking
公开(公告)号：US20240349515A1
公开(公告)日：2024-10-17
申请号：US18755693
申请日：2024-06-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Shu-Ru Wang , Yu-Tse Kuo , Chang-Hung Chen , Yi-Ting Wu , Shu-Wei Yeh , Ya-Lan Chiou , Chun-Hsien Huang
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.
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公开(公告)号：US20230197153A1
公开(公告)日：2023-06-22
申请号：US17580591
申请日：2022-01-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Yu-Tse Kuo , Shu-Ru Wang , Chun-Hsien Huang , Hsin-Chih Yu , Meng-Ping Chuang , Li-Ping Huang , Yu-Fang Chen
IPC: G11C15/04
CPC classification number: G11C15/04
Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.
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公开(公告)号：US20230020795A1
公开(公告)日：2023-01-19
申请号：US17952337
申请日：2022-09-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Shu-Ru Wang , Yu-Tse Kuo , Chang-Hung Chen , Yi-Ting Wu , Shu-Wei Yeh , Ya-Lan Chiou , Chun-Hsien Huang
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
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公开(公告)号：US20220238158A1
公开(公告)日：2022-07-28
申请号：US17179418
申请日：2021-02-19
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Hsien Huang , Yu-Tse Kuo , Shu-Ru Wang , Chun-Yen Tseng , Chun-Chieh Chang
IPC: G11C15/04
Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.
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公开(公告)号：US10522551B2
公开(公告)日：2019-12-31
申请号：US15884063
申请日：2018-01-30
Applicant: United Microelectronics Corp.
Inventor： Chun-Hsien Huang , Ching-Cheng Lung , Yu-Tse Kuo , Chang-Hung Chen , Shu-Ru Wang , Wei-Chi Lee , Chun-Yen Tseng
IPC: H01L27/11 , H01L27/092 , G11C11/41 , H01L23/522 , H01L27/02
Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.
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