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11.发明申请METHOD FOR FABRICATING SUBSTRATE OF SEMICONDUCTOR DEVICE INCLUDING EPITAXIAL LAYER AND SILICON LAYER HAVING SAME CRYSTALLINE ORIENTATION 有权用于制造包括外延层的半导体器件的衬底和具有相同晶体取向的硅层的方法公开(公告)号：US20170040346A1
公开(公告)日：2017-02-09
申请号：US15296027
申请日：2016-10-17
发明人： Wen-Yin Weng , Cheng-Tung Huang , Ya-Ru Yang , Yi-Ting Wu , Yu-Ming Lin , Jen-Yu Wang
IPC分类号： H01L27/12 , H01L21/8234 , H01L21/762 , H01L29/66 , H01L21/308 , H01L29/165 , H01L29/16 , H01L21/84 , H01L21/02
CPC分类号： H01L27/1207 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02381 , H01L21/02433 , H01L21/02529 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L21/3081 , H01L21/76251 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/1054 , H01L29/16 , H01L29/1608 , H01L29/165 , H01L29/66553 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.
摘要翻译： 一种制造半导体器件的衬底的方法包括以下步骤：提供第一硅层; 在所述第一硅层上形成介电层; 将第二硅层接合到介电层; 去除所述第二硅层的一部分和所述介电层的一部分以限定所述第一硅层上的第一区域和第二区域，其中所述第二硅层和所述介电层的剩余部分位于所述第二区域上; 以及在所述第一硅层的所述第一区上形成外延层，其中所述外延层和所述第二硅层包含相同的晶体取向。
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公开(公告)号：US11955154B2
公开(公告)日：2024-04-09
申请号：US17744746
申请日：2022-05-16
发明人： Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yi-Ting Wu , Yung-Ching Hsieh , Jian-Jhong Chen , Chia-Wei Lee
CPC分类号： G11C11/1673
摘要： A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
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公开(公告)号：US20220020745A1
公开(公告)日：2022-01-20
申请号：US17492687
申请日：2021-10-04
发明人： Yen-Wei Tung , Jen-Yu Wang , Cheng-Tung Huang , Yan-Jou Chen
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/66 , H01L21/3213 , H01L21/762 , H01L21/02 , H01L29/06 , H01L27/02 , H01L29/78
摘要： A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.
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公开(公告)号：US10483264B2
公开(公告)日：2019-11-19
申请号：US15660970
申请日：2017-07-27
发明人： Yen-Wei Tung , Jen-Yu Wang , Cheng-Tung Huang , Yan-Jou Chen
IPC分类号： H01L27/092 , H01L29/66 , H01L29/06 , H01L29/78 , H01L29/49 , H01L29/51 , H01L29/423 , H01L29/165 , H01L21/8238 , H01L21/3213 , H01L21/762 , H01L21/02 , H01L27/02
摘要： A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
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公开(公告)号：US09722093B1
公开(公告)日：2017-08-01
申请号：US15253896
申请日：2016-09-01
发明人： Su Xing , Hsueh-Wen Wang , Chien-Yu Ko , Yu-Cheng Tung , Jen-Yu Wang , Cheng-Tung Huang , Yu-Ming Lin
IPC分类号： H01L21/28 , H01L29/786 , H01L29/51 , H01L29/06 , H01L29/423 , H01L29/66 , H01L27/11585
CPC分类号： H01L29/7869 , H01L21/28291 , H01L27/11585 , H01L29/0649 , H01L29/4236 , H01L29/4908 , H01L29/516 , H01L29/66545 , H01L29/6684 , H01L29/66969
摘要： An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.
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16.发明公开公开(公告)号：US20230282260A1
公开(公告)日：2023-09-07
申请号：US17701703
申请日：2022-03-23
发明人： Jian-Jhong Chen , Yi-Ting Wu , Jen-Yu Wang , Cheng-Tung Huang , Po-Chun Yang , Yung-Ching Hsieh
CPC分类号： G11C11/161 , H01L43/02 , H01L43/12 , H01L43/10 , H01L43/08 , H01L27/222
摘要： A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.
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公开(公告)号：US11699705B2
公开(公告)日：2023-07-11
申请号：US17677983
申请日：2022-02-22
发明人： Yen-Wei Tung , Jen-Yu Wang , Cheng-Tung Huang , Yan-Jou Chen
IPC分类号： H01L27/092 , H01L29/66 , H01L29/06 , H01L27/02 , H01L29/78 , H01L29/49 , H01L29/51 , H01L29/423 , H01L29/165 , H01L21/8238 , H01L21/3213 , H01L21/762 , H01L21/02
CPC分类号： H01L27/0924 , H01L21/0217 , H01L21/32139 , H01L21/76224 , H01L21/823821 , H01L21/823842 , H01L21/823878 , H01L27/0207 , H01L27/0922 , H01L29/0649 , H01L29/66545 , H01L29/7848 , H01L29/165 , H01L29/42364 , H01L29/42376 , H01L29/4916 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.
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公开(公告)号：US20220263012A1
公开(公告)日：2022-08-18
申请号：US17735094
申请日：2022-05-02
发明人： Yi-Ting Wu , Yan-Jou Chen , Cheng-Tung Huang , Jen-Yu Wang , Po-Chun Yang , Yung-Ching Hsieh , Jian-Jhong Chen , Bo-Chang Li
摘要： A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
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19.发明授权公开(公告)号：US11171137B2
公开(公告)日：2021-11-09
申请号：US16594054
申请日：2019-10-06
发明人： Yen-Wei Tung , Jen-Yu Wang , Cheng-Tung Huang , Yan-Jou Chen
IPC分类号： H01L21/8238 , H01L29/66 , H01L21/3213 , H01L21/762 , H01L21/02 , H01L29/06 , H01L29/78 , H01L29/49 , H01L29/51 , H01L29/423 , H01L29/165 , H01L27/092 , H01L27/02
摘要： A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
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公开(公告)号：US20190006360A1
公开(公告)日：2019-01-03
申请号：US15660970
申请日：2017-07-27
发明人： Yen-Wei Tung , Jen-Yu Wang , Cheng-Tung Huang , Yan-Jou Chen
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/66 , H01L21/3213 , H01L21/762 , H01L21/02 , H01L29/06 , H01L27/02
摘要： A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
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