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    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
    11.
    发明申请
    NON-VOLATILE MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    非易失性存储器结构及其制造方法

    公开(公告)号：US20140175531A1

    公开(公告)日：2014-06-26

    申请号：US13723159

    申请日：2012-12-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Huang ,  Shen-De Wang ,  Wen-Chung Chang ,  Feng-Ji Tsai ,  Chien-Hung Chen

    IPC: H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/66833 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/792

    Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.

    Abstract translation: 一种用于制造非易失性存储结构的方法包括提供具有栅极结构的衬底，执行第一氧化工艺以形成至少覆盖导电层的底角的第一SiO层，执行第一蚀刻工艺以除去第一 SiO层和所述电介质层的一部分以形成空腔，执行第二氧化工艺以形成覆盖所述空腔的侧壁的第二SiO层和覆盖所述衬底的表面的第三SiO层，形成填充在所述腔中的第一SiN层 并且覆盖衬底上的栅极结构，并且去除第一SiN层的一部分以形成SiN结构，其包括填充在空腔中的脚部和从脚部向上延伸的勃起部，以及覆盖侧壁的安装部 门结构。

    Method for forming resistive random-access memory device
    12.
    发明授权
    Method for forming resistive random-access memory device 有权

    公开(公告)号：US12156487B2

    公开(公告)日：2024-11-26

    申请号：US18382055

    申请日：2023-10-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

    IPC: H10N70/00 ,  H10B63/00

    Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11990546B2

    公开(公告)日：2024-05-21

    申请号：US18120995

    申请日：2023-03-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Cheng-Hua Yang ,  Chih-Chien Chang ,  Shen-De Wang

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423

    CPC classification number: H01L29/7816 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42368

    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

    Memory device and method for fabricating the same
    16.
    发明授权
    Memory device and method for fabricating the same 有权

    公开(公告)号：US11387337B2

    公开(公告)日：2022-07-12

    申请号：US17134131

    申请日：2020-12-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

    IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

    Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

    SEMICONDUCTOR DEVICE
    17.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200043791A1

    公开(公告)日：2020-02-06

    申请号：US16116730

    申请日：2018-08-29

    Applicant: United Microelectronics Corp.

    Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

    Method for forming a semiconductor device
    18.
    发明授权
    Method for forming a semiconductor device 有权

    公开(公告)号：US10312249B2

    公开(公告)日：2019-06-04

    申请号：US15808019

    申请日：2017-11-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Chuan Sun ,  Wei Ta ,  Wang Xiang

    IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/266 ,  H01L29/788

    Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.

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