公开(公告)号：US20170077110A1

公开(公告)日：2017-03-16

申请号：US14924525

申请日：2015-10-27

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Yi-Shan Chiu ,  Wei Ta

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.

Abstract translation: 提供了包括存储器栅极结构和选择栅极结构的半导体器件。 存储器栅极结构与选择栅极结构紧密相邻。 此外，由绝缘层封装的气隙设置在存储器栅极结构和选择栅极结构之间。

公开(公告)号：US09455322B1

公开(公告)日：2016-09-27

申请号：US14862118

申请日：2015-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Weichang Liu ,  Wei Ta ,  Zhen Chen ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/788 ,  H01L27/115 ,  H01L29/51

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.

Abstract translation: 闪光单元形成工艺包括以下步骤。 在基板上形成第一栅极。 第一间隔件形成在第一栅极的一侧，其中第一间隔件包括底部和顶部。 底部被去除，从而形成底切。 在第一间隔物旁边形成第一选择栅，并填入底切。 本发明还提供了一种由所述闪存单元形成工艺形成的闪光单元。 闪存单元包括第一栅极，第一间隔物和第一选择栅极。 第一栅极设置在基板上。 第一间隔件设置在第一栅极的一侧，其中第一间隔件在底部具有底切，因此露出基板。 第一选择栅设置在第一间隔物旁边并延伸到底切中。

公开(公告)号：US09362125B2

公开(公告)日：2016-06-07

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。

公开(公告)号：US20150206894A1

公开(公告)日：2015-07-23

申请号：US14158875

申请日：2014-01-20

Applicant: United Microelectronics Corp.

Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

IPC: H01L27/115 ,  H01L23/00

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。