公开(公告)号：US10262982B2

公开(公告)日：2019-04-16

申请号：US15785447

申请日：2017-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsien Hsu ,  Chien-Fu Chen ,  Cheng-Yang Tsai ,  Wei-Jen Wang ,  Chao-Wei Lin ,  Zhi-Hong Huang ,  Cheng-Tsung Ku ,  Chin-Sheng Yang

IPC: H01L27/02 ,  H03K19/0948 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/167 ,  H03K19/20

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

公开(公告)号：US09905562B2

公开(公告)日：2018-02-27

申请号：US15484126

申请日：2017-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

公开(公告)号：US09673145B2

公开(公告)日：2017-06-06

申请号：US14859367

申请日：2015-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L29/82 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06 ,  H01L23/522 ,  H01L23/00 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.

公开(公告)号：US20160329276A1

公开(公告)日：2016-11-10

申请号：US14859367

申请日：2015-09-21

Applicant: United Microelectronics Corp.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry CHE JEN HU ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L23/528 ,  H01L27/088 ,  H01L27/115 ,  H01L23/522 ,  H01L23/00 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.

Abstract translation: 半导体集成电路布局结构包括第一有源区，与第一有源区隔离的第二有源区，跨过第一有源区和第二有源区的栅极结构以及多个导电结构。 栅极结构的两个相对侧的第一有源区分别形成第一源极区域和第一漏极区域。 栅极结构的两个相对侧的第二有源区分别形成第二源极区和第二漏极区。 导电结构包括多个槽型导电结构和一个岛型导电结构。 槽型导电结构分别形成在第一源极区域，第一漏极区域，第二源极区域和第二漏极区域上。 岛型导电结构形成在栅极结构上。

公开(公告)号：US20230095481A1

公开(公告)日：2023-03-30

申请号：US17517642

申请日：2021-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: H01L27/02

Abstract: An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.

公开(公告)号：US20210288634A1

公开(公告)日：2021-09-16

申请号：US16847682

申请日：2020-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Yuan-Hui Chen ,  Cheng-Yang Tsai ,  Ruei-Yau Chen ,  Cheng-Tsung Ku ,  Zhi-Hong Huang ,  Yu-Lin Chen

IPC: H03K5/13

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

公开(公告)号：US20180151571A1

公开(公告)日：2018-05-31

申请号：US15361479

申请日：2016-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Xing Hua Zhang ,  Shan Liu ,  RUNSHUN WANG ,  Chien-Fu Chen ,  Wei-Jen Wang ,  Chen-Hsien Hsu

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06

Abstract: The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.

公开(公告)号：US20170221897A1

公开(公告)日：2017-08-03

申请号：US15484126

申请日：2017-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry CHE JEN HU ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

公开(公告)号：US09653346B2

公开(公告)日：2017-05-16

申请号：US14800697

申请日：2015-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/7851

Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.

公开(公告)号：US20240290771A1

公开(公告)日：2024-08-29

申请号：US18657811

申请日：2024-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ruei-Yau Chen ,  Wei-Jen Wang ,  Kun-Yuan Wu ,  Chien-Fu Chen ,  Chen-Hsien Hsu

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3≤D3−S, L4≤D4−S, and D3≠D4.