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公开(公告)号：US20180308923A1
公开(公告)日：2018-10-25
申请号：US15927103
申请日：2018-03-21
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L49/02 , H01L27/108 , H01L29/94
CPC classification number: H01L28/82 , H01L27/10808 , H01L27/10855 , H01L28/87 , H01L29/94
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
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公开(公告)号：US20180151666A1
公开(公告)日：2018-05-31
申请号：US15362771
申请日：2016-11-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tri-Rung Yew , Hung-Chan Lin , Li-Wei Feng , Chien-Ting Ho , Chia-Lung Chang
IPC: H01L49/02 , H01L21/311 , H01L21/3205 , H01L27/108
CPC classification number: H01L28/82 , H01L21/31111 , H01L21/32051 , H01L27/10852
Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.
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公开(公告)号：US10903328B2
公开(公告)日：2021-01-26
申请号：US15943717
申请日：2018-04-03
Inventor： Po-Chun Chen , Chia-Lung Chang , Yi-Wei Chen , Wei-Hsin Liu , Han-Yung Tsai
IPC: H01L29/423 , H01L21/28 , H01L27/108 , H01L21/762
Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
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公开(公告)号：US10790289B2
公开(公告)日：2020-09-29
申请号：US16583272
申请日：2019-09-26
Inventor： Chih-Chien Liu , Tzu-Chin Wu , Po-Chun Chen , Chia-Lung Chang
IPC: H01L21/00 , H01L27/108 , H01L21/02 , H01L21/8234
Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
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公开(公告)号：US20190206982A1
公开(公告)日：2019-07-04
申请号：US16297733
申请日：2019-03-11
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L49/02 , H01L27/108 , H01L29/94
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
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Patent Agency Ranking
公开(公告)号：US20180190488A1
公开(公告)日：2018-07-05
申请号：US15859750
申请日：2018-01-02
Inventor： Mei-Ling Chen , Wei-Hsin Liu , Yi-Wei Chen , Ching-Hsiang Chang , Jui-Min Lee , Chia-Lung Chang , Tzu-Chin Wu , Shih-Fang Tzou
IPC: H01L21/02
CPC classification number: H01L21/02532 , H01L21/02422 , H01L21/02592 , H01L21/0262 , H01L21/02664
Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.
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公开(公告)号：US09754943B1
公开(公告)日：2017-09-05
申请号：US15272425
申请日：2016-09-21
Inventor： Kai-Jiun Chang , Yi-Wei Chen , Tsun-Min Cheng , Chih-Chieh Tsai , Wei-Hsin Liu , Jui-Min Lee , Chia-Lung Chang
IPC: H01L21/336 , H01L21/8242 , H01L27/108 , H01L23/528 , H01L23/532 , H01L29/06
CPC classification number: H01L27/10808 , H01L23/528 , H01L23/53271 , H01L23/53295 , H01L27/10823 , H01L27/10876
Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural word lines and plural bit lines. The word lines are disposed in the substrate along a first trench extending along a first direction. Each of the word lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes TiSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof. The bit lines are disposed over the word lines and extended along a second direction across the first direction.
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公开(公告)号：US08927388B2
公开(公告)日：2015-01-06
申请号：US13677318
申请日：2012-11-15
Applicant: United Microelectronics Corp.
Inventor： Jei-Ming Chen , Wen-Yi Teng , Chia-Lung Chang , Chih-Chien Liu
IPC: H01L21/76 , H01L21/762 , H01L21/3105 , H01L21/768 , H01L21/02
CPC classification number: H01L21/76224 , H01L21/02164 , H01L21/3105 , H01L21/76229 , H01L21/76819 , H01L21/76826 , H01L21/76837
Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.
Abstract translation: 制造介电层的方法包括以下步骤。 首先，在基板上形成电介质层，对电介质层进行化学机械研磨（CMP）处理。 随后，在化学机械抛光工艺之后对电介质层进行表面处理工艺，并且表面处理工艺包括引入氧等离子体。
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公开(公告)号：US10811272B2
公开(公告)日：2020-10-20
申请号：US16261578
申请日：2019-01-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wei-Hsin Liu , Ta-Wei Chiu , Chia-Lung Chang , Po-Chun Chen , Hong-Yi Fang , Yi-Wei Chen
IPC: H01L21/3105 , H01L21/027 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L27/108 , H01L29/66
Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
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公开(公告)号：US20190280095A1
公开(公告)日：2019-09-12
申请号：US15943717
申请日：2018-04-03
Inventor： Po-Chun Chen , Chia-Lung Chang , Yi-Wei Chen , Wei-Hsin Liu , Han-Yung Tsai
IPC: H01L29/423 , H01L21/762 , H01L27/108 , H01L21/28
Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
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