公开(公告)号：US11495510B2

公开(公告)日：2022-11-08

申请号：US16780639

申请日：2020-02-03

Applicant: United Microelectronics Corp.

Inventor： Yu-Yuan Huang ,  Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Kai-Kuang Ho ,  Kuang-Hui Tang

IPC: H01L23/31 ,  H01L23/58 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

公开(公告)号：US20160190077A1

公开(公告)日：2016-06-30

申请号：US14609412

申请日：2015-01-29

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuang Ho ,  Chen-Hsiao Wang ,  Yi-Feng Hsu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0312 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad disposed on the substrate, an insulating layer covering the substrate and an edge of the metal pad, wherein at least one recess is disposed within the insulating layer and a first UBM layer contacts the metal pad. The recess is adjacent to the metal pad and the recess is in the shape of a ring. The first UBM layer contacts part of the recess.

Abstract translation: 提供具有凸块下金属化（UBM）层的半导体结构。 半导体结构至少包括衬底，设置在衬底上的金属焊盘，覆盖衬底的绝缘层和金属焊盘的边缘，其中至少一个凹部设置在绝缘层内，第一UBM层与金属接触 垫。 凹槽与金属垫相邻，凹槽呈环形。 第一UBM层接触凹部的一部分。

公开(公告)号：US20240128168A1

公开(公告)日：2024-04-18

申请号：US17985912

申请日：2022-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Feng Lee ,  Chen-Hsiao Wang ,  Kai-Kuang Ho

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49548 ,  H01L23/49579 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48249 ,  H01L2224/48257 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2924/182

Abstract: A QFN package includes a copper lead frame. The copper lead frame includes a die paddle. A die is fixed on the die pad. A coolant passage is disposed within the die paddle. An inlet passage connects to one end of the coolant passage. An outlet passage connects to another end of the coolant passage. A mold compound encapsulates the copper lead frame and the die.

公开(公告)号：US20240120316A1

公开(公告)日：2024-04-11

申请号：US17989635

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuang Ho ,  Yu-Jie Lin ,  Yi-Feng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/16225

Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.

公开(公告)号：US20240014158A1

公开(公告)日：2024-01-11

申请号：US17898478

申请日：2022-08-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Hsiao Wang ,  Kai-Kuang Ho

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49866 ,  H01L21/4853 ,  H01L21/4857 ,  H01L2924/35121 ,  H01L2224/13541 ,  H01L2224/1357 ,  H01L2224/13564 ,  H01L2224/13611 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13014 ,  H01L2224/13011 ,  H01L2224/13552 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/11462 ,  H01L21/563

Abstract: A copper pillar bump (CPB) structure is provided in the present invention, including a substrate, a pad on the substrate, a passivation layer covering the substrate and exposing the pad, and a copper pillar on the passivation layer and the pad and connecting directly with the pad. The copper pillar is provided with an upper part and a lower part, and a top surface of the lower part includes a first top surface and a second top surface. The second top surface is on one side of the first top surface, and the upper part of the copper pillar is on the first top surface of the lower part. A metal bump is on the copper pillar, wherein parts of the metal bump directly contact the second top surface of the lower part.

公开(公告)号：US20210202340A1

公开(公告)日：2021-07-01

申请号：US16780639

申请日：2020-02-03

Applicant: United Microelectronics Corp.

Inventor： YU-YUAN HUANG ,  Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Kai-Kuang Ho ,  Kuang-Hui Tang

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/58

Abstract: A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

公开(公告)号：US09502366B2

公开(公告)日：2016-11-22

申请号：US14609412

申请日：2015-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuang Ho ,  Chen-Hsiao Wang ,  Yi-Feng Hsu

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0312 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad disposed on the substrate, an insulating layer covering the substrate and an edge of the metal pad, wherein at least one recess is disposed within the insulating layer and a first UBM layer contacts the metal pad. The recess is adjacent to the metal pad and the recess is in the shape of a ring. The first UBM layer contacts part of the recess.

Abstract translation: 提供具有凸块下金属化（UBM）层的半导体结构。 半导体结构至少包括衬底，设置在衬底上的金属焊盘，覆盖衬底的绝缘层和金属焊盘的边缘，其中至少一个凹部设置在绝缘层内，第一UBM层与金属接触 垫。 凹槽与金属垫相邻，凹槽呈环形。 第一UBM层接触凹部的一部分。