公开(公告)号：US20240315095A1

公开(公告)日：2024-09-19

申请号：US18135741

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Yi-Feng Hsu

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

公开(公告)号：US20240413136A1

公开(公告)日：2024-12-12

申请号：US18223539

申请日：2023-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Kai Yu ,  Chen-Hsiao Wang ,  Yi-Feng Hsu ,  Kai-Kuang Ho

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

Abstract: The present invention provides a 3D integrated circuit structure formed by stacking semiconductor structures. The semiconductor structures form a multi-die heterogeneous 3D packaging by direct bonding the bonding pads of re-distribution layers. The same or different dies are used to produce the semiconductor structures through the back-end packaging process, and then hybrid bonding technology is used to stack and interconnect the semiconductor structures. The position of the bonding pad can be redefined by re-distribution layer, thereby overcoming the limitations of chip bonding pad position, chip size and quantity.

公开(公告)号：US20240014082A1

公开(公告)日：2024-01-11

申请号：US17891090

申请日：2022-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Feng Hsu

IPC: H01L23/13 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L23/3672 ,  H01L23/3733 ,  H01L21/4871

Abstract: The invention provides a semiconductor structure, which comprises a chip comprising a substrate, wherein the substrate has a front surface and a back surface, and the front surface of the substrate comprises a circuit layer, the back surface of the substrate comprises a plurality of microstructures, and a thermal interface material located on the back surface of the substrate, and the thermal interface material contacts the microstructures directly.

公开(公告)号：US20240120316A1

公开(公告)日：2024-04-11

申请号：US17989635

申请日：2022-11-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuang Ho ,  Yu-Jie Lin ,  Yi-Feng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/08145 ,  H01L2224/16225

Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.

公开(公告)号：US09502366B2

公开(公告)日：2016-11-22

申请号：US14609412

申请日：2015-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuang Ho ,  Chen-Hsiao Wang ,  Yi-Feng Hsu

IPC: H01L23/52 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0312 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad disposed on the substrate, an insulating layer covering the substrate and an edge of the metal pad, wherein at least one recess is disposed within the insulating layer and a first UBM layer contacts the metal pad. The recess is adjacent to the metal pad and the recess is in the shape of a ring. The first UBM layer contacts part of the recess.

Abstract translation: 提供具有凸块下金属化（UBM）层的半导体结构。 半导体结构至少包括衬底，设置在衬底上的金属焊盘，覆盖衬底的绝缘层和金属焊盘的边缘，其中至少一个凹部设置在绝缘层内，第一UBM层与金属接触 垫。 凹槽与金属垫相邻，凹槽呈环形。 第一UBM层接触凹部的一部分。

公开(公告)号：US20240429093A1

公开(公告)日：2024-12-26

申请号：US18224576

申请日：2023-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Kai-Kuang Ho ,  Chuan-Lan Lin ,  Yu-Ping Wang ,  Chu-Fu Lin ,  Yi-Feng Hsu ,  Yu-Jie Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/784 ,  H01L23/544

Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.

公开(公告)号：US20240222204A1

公开(公告)日：2024-07-04

申请号：US18163293

申请日：2023-02-02

Applicant: United Microelectronics Corp.

Inventor： Yu-Yuan Huang ,  Kai-Kuang Ho ,  Yi-Feng Hsu

IPC: H01L21/66 ,  H01L23/48 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L22/32 ,  H01L23/481 ,  H01L29/2003 ,  H01L29/7786

Abstract: Provided is a semiconductor device including a substrate, a semiconductor layer, a source electrode, a first metal layer, a backside via hole, and a backside metal layer. The substrate has a frontside and a backside opposite to each other. The semiconductor layer is disposed on the frontside of the substrate. The source electrode is disposed on the semiconductor layer. The first metal layer is disposed on the source electrode. The backside via hole extends from the backside of the substrate to a bottom surface of the first metal layer. The backside via hole is laterally separated from the source electrode by a non-zero distance. The backside metal layer is disposed on the backside of the substrate and extending to cover a surface of the backside via hole.

公开(公告)号：US20240120306A1

公开(公告)日：2024-04-11

申请号：US17980571

申请日：2022-11-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuang Ho ,  Yu-Jie Lin ,  Yi-Feng Hsu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L23/4985 ,  H01L24/08 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/08238 ,  H01L2224/32054 ,  H01L2224/32225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/83203 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06568 ,  H01L2924/15151 ,  H01L2924/182

Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.

公开(公告)号：US20160190077A1

公开(公告)日：2016-06-30

申请号：US14609412

申请日：2015-01-29

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuang Ho ,  Chen-Hsiao Wang ,  Yi-Feng Hsu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0312 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor structure with an under bump metallization (UBM) layer is provided. The semiconductor structure at least includes a substrate, a metal pad disposed on the substrate, an insulating layer covering the substrate and an edge of the metal pad, wherein at least one recess is disposed within the insulating layer and a first UBM layer contacts the metal pad. The recess is adjacent to the metal pad and the recess is in the shape of a ring. The first UBM layer contacts part of the recess.

Abstract translation: 提供具有凸块下金属化（UBM）层的半导体结构。 半导体结构至少包括衬底，设置在衬底上的金属焊盘，覆盖衬底的绝缘层和金属焊盘的边缘，其中至少一个凹部设置在绝缘层内，第一UBM层与金属接触 垫。 凹槽与金属垫相邻，凹槽呈环形。 第一UBM层接触凹部的一部分。