公开(公告)号：US20160204230A1

公开(公告)日：2016-07-14

申请号：US15077937

申请日：2016-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/02 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.

Abstract translation: 公开了半导体器件的制造方法。 优选地，使用两个硬掩模来限定第一栅极的宽度（可用于控制栅极）和第二栅极的宽度（可用于选择栅极）。 因此，宽度被很好地控制。 例如，在一个实施例中，可以根据需要预先调整选择栅极的宽度，并且在蚀刻工艺期间由第二硬掩模保护选择栅极，以便获得选择栅极，其上部具有适当的 宽度。 因此，半导体器件在小型化时仍然具有优异的性能。

公开(公告)号：US09202701B1

公开(公告)日：2015-12-01

申请号：US14572805

申请日：2014-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-I Chou ,  Chi-Cheng Huang ,  Yu-Chun Chang ,  Ling-Hsiu Chou ,  Tseng-Fang Dai ,  Jheng-Jie Huang ,  Ping-Chia Shih

IPC: H01L21/336 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.

Abstract translation: 一种用于制造氧化硅 - 氮化物 - 氧化物 - 硅非易失性存储单元的方法包括以下步骤。 在衬底中形成植入区域。 形成第一氧化物层，氮化物层和第二氧化物层并堆叠在基板上。 第二氧化物层的密度高于第一氧化物层的密度。 第一光致抗蚀剂图案形成在第二氧化物层上并对应于植入区域。 然后进行第一湿法蚀刻工艺以形成氧​​化物硬掩模。 执行第二湿法蚀刻工艺以去除由氧化物硬掩模暴露的氮化物层以形成氮化物图案。 然后进行清洁处理以除去由氮化物图案暴露的氧化物硬掩模和第一氧化物层，然后在氮化物图案上形成栅极氧化物层。

公开(公告)号：US20140353739A1

公开(公告)日：2014-12-04

申请号：US13909057

申请日：2013-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L29/66 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.

Abstract translation: 一种半导体器件，包括彼此紧邻的第一栅极结构和第二栅极结构，其间具有间隔物。 第二栅极结构的顶部的线宽不小于其底部的线宽。 还公开了其制造方法。 通过蚀刻穿过第一硬掩模形成瞬态第一栅极结构和临时栅极结构。 第二栅极结构形成在第一间隔物和彼此相对的第二间隔物之间​​，分别设置在瞬态第一栅极结构和临时栅极结构上。 第二个门结构用第二个硬掩模覆盖。 通过图案化的光致抗蚀剂层进行蚀刻处理以去除暴露的第一硬掩模和临时栅极结构，并且部分地去除第一硬掩模和瞬态第一栅极结构的暴露部分以形成第一栅极结构。

公开(公告)号：US11758720B2

公开(公告)日：2023-09-12

申请号：US18077183

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US20230260827A1

公开(公告)日：2023-08-17

申请号：US17687692

申请日：2022-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Che-Hao Kuo ,  Ssu-Yin Liu ,  Ching-Hua Yeh ,  I-Hsin Sung

IPC: H01L21/762 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3115 ,  H01L23/00

CPC classification number: H01L21/76224 ,  H01L21/32139 ,  H01L21/31144 ,  H01L21/31155 ,  H01L23/573

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

公开(公告)号：US11552088B2

公开(公告)日：2023-01-10

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US20210217708A1

公开(公告)日：2021-07-15

申请号：US16741756

申请日：2020-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Lin Wang ,  Ping-Chia Shih ,  Ming-Che Tsai ,  Kuei-Ya Chuang ,  Yi-Chun Teng ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/768

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

公开(公告)号：US10580780B2

公开(公告)日：2020-03-03

申请号：US16005422

申请日：2018-06-11

Applicant: United Microelectronics Corp.

Inventor： Zi-Jun Liu ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Hung-Wei Lin ,  An-Hsiu Cheng ,  Chih-Hao Pan ,  Cheng-Hua Chou ,  Chih-Hung Wang

IPC: H01L23/62 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/1156 ,  H01L21/762 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/28

Abstract: Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

公开(公告)号：US10340282B1

公开(公告)日：2019-07-02

申请号：US15895886

申请日：2018-02-13

Applicant: United Microelectronics Corp.

Inventor： Shu-Hung Yu ,  Chun-Hung Cheng ,  Chuan-Fu Wang ,  An-Hsiu Cheng ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Chia-Hui Huang ,  Chih-Yao Wang ,  Zi-Jun Liu ,  Chih-Hao Pan

IPC: H01L21/18 ,  H01L27/1157 ,  H01L21/762 ,  H01L23/528 ,  H01L29/06

Abstract: A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.

公开(公告)号：US10312250B1

公开(公告)日：2019-06-04

申请号：US15878278

申请日：2018-01-23

Applicant: United Microelectronics Corp.

Inventor： Hsuan-Chun Tseng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chi-Cheng Huang ,  Ping-Chia Shih

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11534 ,  H01L27/11573 ,  H01L27/11578

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.