中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.015 seconds)

    Semiconductor device with magnetic tunnel junction
    11.
    发明授权
    Semiconductor device with magnetic tunnel junction 有权

    公开(公告)号：US10944048B2

    公开(公告)日：2021-03-09

    申请号：US16554531

    申请日：2019-08-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang

    IPC: H01L43/08 ,  H01L43/02 ,  H01L27/22

    Abstract: A semiconductor device includes a substrate, an array of magnetic tunnel junctions (MTJs), an array of first dummy MTJs, and an array of second dummy MTJs. The substrate includes an array region defined thereon, and the array region includes at least an outermost corner. The array of MTJs is disposed in the array region. The array of the first dummy MTJs is disposed along the outermost corner of the array region. The array of the second dummy MTJs is disposed around the array region and the array of first dummy MTJs.

    Magnetic memory cell
    12.
    发明授权
    Magnetic memory cell 有权

    公开(公告)号：US10930704B2

    公开(公告)日：2021-02-23

    申请号：US16812354

    申请日：2020-03-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Rai-Min Huang ,  Hung-Yueh Chen ,  Ya-Huei Tsai ,  Yu-Ping Wang

    IPC: H01L27/22 ,  H01L23/532 ,  H01L43/02 ,  H01L23/522 ,  H01L23/528 ,  G11C11/16

    Abstract: A magnetic memory cell includes a substrate, a transistor, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane and the first horizontal plane are not coplanar.

    SEMICONDUCTOR DEVICE HAVING METAL GATE
    13.
    发明申请
    SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
    具有金属门的半导体器件

    公开(公告)号：US20170047330A1

    公开(公告)日：2017-02-16

    申请号：US15339945

    申请日：2016-11-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Ming Lai ,  Ya-Huei Tsai

    IPC: H01L27/092 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/82345 ,  H01L21/8238 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    Abstract: A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer. The second metal gate structure includes the gate insulating layer, a second bottom barrier layer, the top barrier layer, and the metal layer on the substrate in order, wherein the top barrier layer is directly in contact with the second bottom barrier layer. The first bottom barrier layer and the second bottom barrier layer have different impurity compositions.

    Abstract translation: 具有金属栅极的半导体器件分别包括设置在第一器件区域中的第一金属栅极结构和设置在衬底上的第二器件区域中的第二金属栅极结构。 第一金属栅极结构依次包括栅极绝缘层，第一底部阻挡层，顶部阻挡层和设置在基板上的金属层，其中顶部阻挡层直接与第一底部阻挡层接触。 第二金属栅极结构依次包括栅极绝缘层，第二底部阻挡层，顶部阻挡层和金属层，其中顶部阻挡层直接与第二底部阻挡层接触。 第一底部阻挡层和第二底部阻挡层具有不同的杂质组成。

    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    15.
    发明申请
    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20250040149A1

    公开(公告)日：2025-01-30

    申请号：US18916730

    申请日：2024-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

    Layout pattern for magnetoresistive random access memory
    16.
    发明授权
    Layout pattern for magnetoresistive random access memory 有权

    公开(公告)号：US12150315B2

    公开(公告)日：2024-11-19

    申请号：US18395649

    申请日：2023-12-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01L23/528 ,  H10N50/80 ,  H10N50/85

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    20.
    发明申请
    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20220285437A1

    公开(公告)日：2022-09-08

    申请号：US17750386

    申请日：2022-05-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

    IPC: H01L27/22 ,  H01L23/528 ,  H01L43/02

    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

Patent Agency Ranking