公开(公告)号：US20170179295A1

公开(公告)日：2017-06-22

申请号：US15447081

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78603

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

公开(公告)号：US20170155861A1

公开(公告)日：2017-06-01

申请号：US14953411

申请日：2015-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Chen-Bin Lin ,  Ding-Lung Chen

IPC: H04N5/378 ,  H04N5/225 ,  H04N9/04

CPC classification number: H04N5/374 ,  H01L27/14667 ,  H01L31/035218 ,  H04N5/3745 ,  H04N9/04

Abstract: An operating method of an image sensor includes the following steps. The image sensor includes at least one pixel unit. The pixel unit includes a photoelectric conversion unit, a first control unit, a capacitor unit, and a sensing unit. The photoelectric conversion unit includes a quantum film photoelectric conversion unit, and the first control unit includes an oxide semiconductor transistor. The capacitor unit is coupled to the first control unit, and the sensing unit is configured to sense signals at a sense point coupled between the first control unit and the sensing unit. The pixel unit is discharged before a readout operation. The capacitor unit is charged by electrons emitted from the photoelectric conversion unit when the photoelectric conversion unit is excited by light. Signals at the sense point are then sensed by the sensing unit.

公开(公告)号：US20170084614A1

公开(公告)日：2017-03-23

申请号：US14856565

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Hui Wu ,  ZHIBIAO ZHOU ,  HAI BIAO YAO ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10832 ,  H01L27/10867 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: A memory cell includes a substrate, a deep trench (DT) capacitor formed in the substrate, at least an insulting layer formed on the substrate, and an oxide semiconductor field effect transistor (OS FET) device formed on the insulating layer. And more important, the OS FET device is electrically connected to the DT capacitor.

公开(公告)号：US20150137323A1

公开(公告)日：2015-05-21

申请号：US14080798

申请日：2013-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure.

Abstract translation: 公开了一种通过硅通孔（TSV）制造方法。 该方法包括以下步骤：提供衬底; 在衬底中形成穿硅通孔（TSV）; 在TSV中沉积衬垫; 移除TSV底部的衬垫; 以及在TSV中填充用于形成TSV结构的第一导电层。

公开(公告)号：US20240021593A1

公开(公告)日：2024-01-18

申请号：US17891116

申请日：2022-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU

IPC: H01L25/16 ,  H01L33/00 ,  H01L33/62 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L33/0095 ,  H01L33/62 ,  H01L33/0093 ,  H01L24/24 ,  H01L2224/24051 ,  H01L2224/245 ,  H01L2933/0066 ,  H01L2924/0549 ,  H01L2224/24147 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01022

Abstract: A light-emitting diode (LED) structure is provided in the present invention, including a substrate, a dielectric layer on the substrate, metal interconnects in the dielectric layer, LED dies on the dielectric layer, wherein each LED die is provided with a front side and a back side, the back side is bonded with the dielectric layer, and the cathode and anode are on the front side of LED die, and bonding lines connecting the cathode and anode on the front side of LED die to the metal interconnects respectively.

公开(公告)号：US20190123052A1

公开(公告)日：2019-04-25

申请号：US15790035

申请日：2017-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU

IPC: H01L27/11 ,  G11C11/412

Abstract: A 6T SRAM cell includes a substrate having thereon a first pull-up (PU-1) transistor, a first pull-down (PD-1) transistor, a second pull-up (PU-2) transistor, and a second pull-down (PD-2) transistor. A first contact hard mask partially overlaps with a source diffusion region of the PU-1 transistor. A second contact hard mask partially overlaps with a first gate and a source diffusion region of the PD-1 transistor. A first contact plug partially lands on the first contact hard mask and partially lands on the source diffusion region of the PU-1 transistor. A second contact plug partially lands on the second contact hard mask and partially lands on the source diffusion region of the PD-1 transistor.

公开(公告)号：US20180352176A1

公开(公告)日：2018-12-06

申请号：US15613147

申请日：2017-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU

IPC: H04N5/347 ,  H04N5/232 ,  H04N5/369 ,  H04N5/378

CPC classification number: H04N5/347 ,  H04N5/23245 ,  H04N5/3696 ,  H04N5/378

Abstract: An image sensor includes a first pixel and a second pixel. The first pixel receives a first signal sensed by a first photodiode. The second pixel receives a second signal sensed by a second photodiode. A pixel binning device includes a first transistor, a second transistor and a binning circuit, wherein the first transistor switchably couples to the first pixel to transfer the first signal, the second transistor switchably couples to the second pixel to transfer the second signal, and the binning circuit couples to the first transistor and the second transistor to bin the first signal and the second signal.

公开(公告)号：US20180331233A1

公开(公告)日：2018-11-15

申请号：US16027386

申请日：2018-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L21/426 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/426 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L29/7869

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, a gate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US20170358582A1

公开(公告)日：2017-12-14

申请号：US15180095

申请日：2016-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen

IPC: H01L27/108 ,  H01L49/02 ,  H01L23/528 ,  H01L29/423 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/10814 ,  H01L23/528 ,  H01L27/10897 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/42356 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged in an array and electrically connected to corresponding bit lines and word lines respectively, and any two memory cells adjacent to each other share a same oxide semiconductor layer as a channel layer. The present invention also relates to a semiconductor memory device including two memory cells sharing a same oxide semiconductor layer as a channel layer.

公开(公告)号：US20170338351A1

公开(公告)日：2017-11-23

申请号：US15191542

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Chen-Bin Lin ,  SANPO WANG ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.