公开(公告)号：US5459097A

公开(公告)日：1995-10-17

申请号：US133818

申请日：1993-10-07

申请人： Cammy R. Abernathy ,  Stephen J. Pearton ,  Fan Ren ,  Patrick W. Wisk

发明人： Cammy R. Abernathy ,  Stephen J. Pearton ,  Fan Ren ,  Patrick W. Wisk

IPC分类号： C23C16/18 ,  C30B23/08 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  H01L21/331 ,  H01L29/205

CPC分类号： H01L29/66318 ,  H01L21/02395 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639

摘要： In accordance with the invention, aluminum-containing layers are grown by molecular beam processes using as an arsenic precursor phenylarsine (PhAs). Because PhAs is more reactive than arsine and less reactive than arsenic, it decomposes selectively on III-V surfaces but not on mask materials. Thus in contrast to conventional processes, growth using PhAs permits selective growth on unmasked gallium arsenide surfaces but inhibits growth on typical mask materials such as silicon nitride.

摘要翻译： 根据本发明，通过使用砷前体苯胂（PhAs）的分子束方法生长含铝层。 因为PhAs比砷更有活性，反应性低于砷，所以它在III-V表面上有选择性地分解，而不是在掩模材料上分解。 因此，与常规方法相比，使用PhAs的生长允许对未掩蔽的砷化镓表面进行选择性生长，但抑制典型掩模材料如氮化硅上的生长。

公开(公告)号：US5176792A

公开(公告)日：1993-01-05

申请号：US783647

申请日：1991-10-28

申请人： Thomas R. Fullowan ,  Stephen J. Pearton ,  Fan Ren

发明人： Thomas R. Fullowan ,  Stephen J. Pearton ,  Fan Ren

IPC分类号： C23F4/00 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213

CPC分类号： C23F4/00 ,  H01L21/28 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139

摘要： The present applicants have discovered that a layer predominantly comprising tungsten can be formed into precise patterns having substantially vertical walls by using titanium as a mask and plasma etching in a fluorine-containing plasma such as CF.sub.4 or SF.sub.6. The success of the process is believed attributable to the occurrence of an etch stop reaction on the sidewalls of the tungsten. The products of the reaction inhibit horizontal etching. After the tungsten is etched, the titanium mask can be selectively removed, as by etching in dilute HF. Each step in the process can be effected without subjecting the workpiece to voltage magnitudes in excess of 200 volts or temperatures outside the range between room temperature and 200.degree. C.

公开(公告)号：US5168071A

公开(公告)日：1992-12-01

申请号：US680953

申请日：1991-04-05

申请人： Thomas R. Fullowan ,  Stephen J. Pearton ,  Fan Ren

发明人： Thomas R. Fullowan ,  Stephen J. Pearton ,  Fan Ren

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/331 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737

CPC分类号： H01L21/3081

摘要： Disclosed is a method of making semiconductor devices that comprises etching of a semiconductor layer, with a patterned metal layer acting as the etch mask. The patterned metal layer comprises a mask metal layer (exemplarily Ti) overlying a contact metal layer (exemplarily a Au-containing layer). In an exemplary embodiment the inventive method is used to manufacture InP-based heterojunction bipolar transistors.

公开(公告)号：US08828713B2

公开(公告)日：2014-09-09

申请号：US12966531

申请日：2010-12-13

申请人： Fan Ren ,  Stephen John Pearton ,  Tanmay Lele

发明人： Fan Ren ,  Stephen John Pearton ,  Tanmay Lele

IPC分类号： G01N27/00

CPC分类号： G01N33/54306 ,  G01N27/4145 ,  G01N33/0045 ,  H01L29/2003 ,  H01L29/7787

摘要： Embodiments of the invention include sensors comprising high electron mobility transistors (HEMTs) with capture reagents on a gate region of the HEMTs. Example sensors include HEMTs with a thin gold layer on the gate region and bound antibodies; a thin gold layer on the gate region and chelating agents; a non-native gate dielectric on the gate region; and nanorods of a non-native dielectric with an immobilized enzyme on the gate region. Embodiments including antibodies or enzymes can have the antibodies or enzymes bound to the Au-gate via a binding group. Other embodiments of the invention are methods of using the sensors for detecting breast cancer, prostate cancer, kidney injury, glucose, metals or pH where a signal is generated by the HEMT when a solution is contacted with the sensor. The solution can be blood, saliva, urine, breath condensate, or any solution suspected of containing any specific analyte for the sensor.

摘要翻译： 本发明的实施例包括在HEMT的栅极区域上具有捕获试剂的高电子迁移率晶体管（HEMT）的传感器。 示例传感器包括在栅极区域上具有薄金层的HEMT和结合的抗体; 栅区上的薄金层和螯合剂; 栅极区域上的非天然栅极电介质; 以及在栅极区域上具有固定化酶的非天然电介质的纳米棒。 包括抗体或酶的实施方案可以具有通过结合基团结合到Au-门的抗体或酶。 本发明的其它实施方案是使用传感器检测乳腺癌，前列腺癌，肾损伤，葡萄糖，金属或pH的方法，当溶液与传感器接触时，HEMT产生信号。 解决方案可以是血液，唾液，尿液，呼吸冷凝液或任何怀疑含有传感器特定分析物的溶液。

公开(公告)号：US20120098599A1

公开(公告)日：2012-04-26

申请号：US13380956

申请日：2010-06-29

申请人： Chih-Yang Chang ,  Fan Ren ,  Stephen John Pearton

发明人： Chih-Yang Chang ,  Fan Ren ,  Stephen John Pearton

IPC分类号： H03F3/21 ,  H01L21/335 ,  H01L29/778 ,  H01L27/088 ,  H01L29/20 ,  H01L29/161

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/517

摘要： An enhancement mode (E-mode) HEMT is provided that can be used for analog and digital applications. In a specific embodiment, the HEMT can be an AlN/GaN HEMT. The subject E-mode device can be applied to high power, high voltage, high temperature applications, including but not limited to telecommunications, switches, hybrid electric vehicles, power flow control and remote sensing. According to an embodiment of the present invention, E-mode devices can be fabricated by performing an oxygen plasma treatment with respect to the gate area of the HEMT. The oxygen plasma treatment can be, for example, an O2 plasma treatment. In addition, the threshold voltage of the E-mode HEMT can be controlled by adjusting the oxygen plasma exposure time. By using a masking layer protecting regions for depletion mode (D-mode) devices, D-mode and E-mode devices can be fabricated on a same chip.

摘要翻译： 提供了可用于模拟和数字应用的增强模式（E模式）HEMT。 在具体实施方式中，HEMT可以是AlN / GaN HEMT。 主题E模式设备可以应用于高功率，高电压，高温应用，包括但不限于电信，交换机，混合动力电动车辆，电力流量控制和遥感。 根据本发明的实施例，可以通过对HEMT的栅极区进行氧等离子体处理来制造E模式器件。 氧等离子体处理可以是例如O 2等离子体处理。 此外，E模式HEMT的阈值电压可以通过调节氧等离子体暴露时间来控制。 通过使用用于耗尽模式（D模式）器件的掩模层保护区域，可以在同一芯片上制造D模式和E模式器件。

公开(公告)号：US20080303121A1

公开(公告)日：2008-12-11

申请号：US11916910

申请日：2006-05-31

申请人： Jenshan Lin ,  Fan Ren ,  Stephen J. Pearton ,  Travis J. Anderson ,  Brent P. Gila

发明人： Jenshan Lin ,  Fan Ren ,  Stephen J. Pearton ,  Travis J. Anderson ,  Brent P. Gila

IPC分类号： H01L23/34 ,  H01L23/50

CPC分类号： H01L23/552 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A multi-layer heatsink module for effecting temperature control in a three-dimensional integrated chip is provided. The module includes a high thermal conductivity substrate having first and second opposing sides, and a gallium nitride (GaN) layer disposed on the first side of the substrate. An integrated array of passive and active elements defining electronic circuitry is formed in the GaN layer. A metal ground plane having first and second opposing sides is disposed on the second side of the substrate, with the first side of the ground plane being adjacent to the second side of the substrate. A dielectric layer of low thermal dielectric material is deposited on the back side of the ground plane, and a metal heatsink is bonded to the dielectric layer. A via extends through the dielectric layer from the metal heatsink to the metal ground plane.

摘要翻译： 提供了一种用于在三维集成芯片中实现温度控制的多层散热模块。 该模块包括具有第一和第二相对侧的高导热性衬底和设置在衬底的第一侧上的氮化镓（GaN）层。 在GaN层中形成限定电子电路的无源和有源元件的集成阵列。 具有第一和第二相对侧的金属接地平面设置在基板的第二侧上，接地平面的第一侧与基板的第二侧相邻。 在接地面的背面侧沉积有低介电常数的电介质层，金属散热片与电介质层接合。 通孔从金属散热器延伸穿过电介质层到金属接地平面。

公开(公告)号：US5903037A

公开(公告)日：1999-05-11

申请号：US804782

申请日：1997-02-24

申请人： Alfred Yi Cho ,  Minghwei Hong ,  James Robert Lothian ,  Joseph Petrus Mannaerts ,  Fan Ren

发明人： Alfred Yi Cho ,  Minghwei Hong ,  James Robert Lothian ,  Joseph Petrus Mannaerts ,  Fan Ren

IPC分类号： H01L29/78 ,  B82B1/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51 ,  H01L21/316 ,  H01L23/58

CPC分类号： H01L29/517 ,  H01L21/28158 ,  H01L21/28264 ,  H01L29/66522 ,  H01L2924/0002

摘要： It has been found that a Ga-oxide-containing layer is substantially not etched in HF solution if the layer is a Ga-Gd-oxide with Gd:Ga atomic ratio of more than about 1:7.5, preferably more than 1:4 or even 1:2. This facilitates removal of a protective dielectric (typically SiO.sub.2) layer after an ohmic contact anneal, with the Ga-Gd-oxide gate oxide layer serving as etch stop and not being adversely affected by contact with the HF etchant. Gd-Ge-oxide also exhibits a composition-dependent etch rate in HCl:H.sub.2 O.

摘要翻译： 已经发现，如果该层是Gd:Ga原子比大于约1:7.5，优选大于1:4的Ga-Gd氧化物，则在HF溶液中基本上不蚀刻含Ga氧化物层，或 甚至1：2。 这有助于在欧姆接触退火之后去除保护性电介质（通常为SiO 2）层，其中Ga-Gd氧化物栅极氧化物层用作蚀刻停止，并且不受与HF蚀刻剂的接触的不利影响。 Gd-Ge-氧化物还表现出在HCl：H 2 O中的组成依赖性蚀刻速率。

公开(公告)号：US5620909A

公开(公告)日：1997-04-15

申请号：US566766

申请日：1995-12-04

申请人： Jenshan Lin ,  James R. Lothian ,  Fan Ren

发明人： Jenshan Lin ,  James R. Lothian ,  Fan Ren

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L23/31 ,  H01L29/423 ,  H01L21/338 ,  H01L21/50 ,  H01L29/812

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L23/3171 ,  H01L29/42316 ,  H01L2924/0002 ,  H01L2924/19041 ,  Y10S438/951 ,  Y10S438/958

摘要： A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.

摘要翻译： 通过ECR-CVD将薄的共形钝化电介质膜沉积在包括半微米器件的IC芯片上，每个半导体器件包括亚微米宽度不规则形状的栅电极。 形成图案化抗蚀剂的保护层，覆盖在每个钝化器件上。 然后通过ECP-CVD在低于抗蚀剂的玻璃化转变温度的温度下在芯片的表面上沉积另外的电介质材料。 随后，在剥离步骤中，将图案化的抗蚀剂与覆盖抗蚀剂的附加电介质材料一起从芯片上去除。

公开(公告)号：US5171704A

公开(公告)日：1992-12-15

申请号：US662550

申请日：1991-02-28

申请人： Cammy R. Abernathy ,  Fan Ren

发明人： Cammy R. Abernathy ,  Fan Ren

IPC分类号： H01L21/203 ,  H01L21/205 ,  H01L21/331 ,  H01L29/205 ,  H01L29/207 ,  H01L29/73 ,  H01L29/737

CPC分类号： H01L29/207 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02631 ,  H01L29/66318 ,  Y10S148/11

摘要： High carrier concentration, as well as abrupt change in such concentration in GaAs-based devices, is the consequence of selection of tin dopant-containing precursor compounds as used during layer growth. Alkyl tin compounds, as used during MetalOrganic Molecular Beam Epitaxy, are of particular value in the growth of pnp heterojunction bipolar transistors, likely in conjunction with other devices in large scale integrated circuits.

公开(公告)号：US4943540A

公开(公告)日：1990-07-24

申请号：US290774

申请日：1988-12-28

申请人： Fan Ren ,  Nitin J. Shah

发明人： Fan Ren ,  Nitin J. Shah

IPC分类号： C23F1/16 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/30612 ,  Y10S148/051 ,  Y10S148/056

摘要： A method for selectively etching higher aluminum concentration AlGaAs in the presence of lower aluminum concentration AlGaAs or GaAs, preferably at room temperature. The AlGaAs is first cleaned with a solution of NH.sub.4 OH and rinsed. The AlGaAs is then etched in a solution of HF. If photoresist is used on the AlGaAs, the photoresist may first be baked to increase the adhesion of the photoresist to the AlGaAs and to "toughen" the photoresist to reduce undercutting thereof. Agitation is applied to the AlGaAs or the etchant to assist in the uniform etching of the AlGaAs.